EPM5192AQC-1 vs EPM5192AQC100-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AQC-1 par Altera et EPM5192AQC100-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AQC-1 | EPM5192AQC100-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,40 | $11,85 |
| Family | MAX 5000 | — |
| Device Type | One-Time Programmable (OTP) CPLD | — |
| Macrocells | 192 | 192 |
| Logic Elements / Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX value] | 66.7 MHz |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs / Outputs | 72 inputs / 64 outputs | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Plage de température de fonctionnement | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Boîtier | PQFP-100 (Plastic Quad Flat Pack) | 100-lead PQFP (R-PQFP-G100) |
| Terminal Pitch | 0.635 mm | 0.65 mm |
| Technology | CMOS, UV-Erasable / OTP EPROM | — |
| Configuration Method | One-Time Programmable (OTP) / UV-Erasable | — |
| Type de montage | Surface Mount | Surface Mount (PQFP) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Device Family | — | MAX 5000 |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Propagation Delay (tpd) | — | 33 ns |
| Process Technology | — | CMOS |
| Programming Technology | — | UV-Erasable / One-Time-Programmable (OTP) |
| Tension d'alimentation | — | 5 V (typical, MAX 5000 family) |
| I/O Count | — | [DATA_NEEDED: usable I/O count] |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |