EPM5192AQC100-15 vs EPM5192AQC-2 Comparaison
Comparaison détaillée côte à côte de EPM5192AQC100-15 par Altera et EPM5192AQC-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AQC100-15 | EPM5192AQC-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $21,50 |
| Manufacturer | Altera (now Intel) | — |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Technology | CMOS | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | 45 ns (-2 speed grade) |
| Total Inputs | 72 | 72 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| External Clock Inputs | 1 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Boîtier | 100-pin PQFP (R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | EPROM (UV-erasable, OTP) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirmed compliance status] |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial / industrial / military grade] |
| Series | — | MAX 5000 (EPM5192) |
| Fréquence d'horloge maximale | — | [DATA_NEEDED: max fMAX for -2 grade] |
| Process Technology | — | CMOS |
| Switch Matrix | — | UV-Erasable / OTP (windowless on AQC package) |
| Lead Pitch | — | 0.635 mm |
| Terminal Form | — | Gull-wing |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary scan |