EPM5192GC-1 vs EPM5192AGC-20 Comparaison
Comparaison détaillée côte à côte de EPM5192GC-1 par Altera et EPM5192AGC-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GC-1 | EPM5192AGC-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,85 | $9,95 |
| Family | MAX 5000 (Classic) | MAX 5000 |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | 12,000 |
| Logic Array Blocks (LABs) | 12 | 8 |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Boîtier | 100-pin Ceramic PGA (GC) | PGA-132 (ceramic windowed, 'GC') |
| Type de montage | Through-Hole (PGA) | Through-hole (PGA socket) |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | 0C to 70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] |
| Device Type | — | EPLD (EEPLD, UV-erasable) |
| Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz (max) |
| Dedicated I/O Pins | — | 96 |
| Programming Interface | — | IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5 V ISP) |
| Security Bit | — | Yes (pattern read-back protected) |