EPM5192GC-1 vs EPM5192GI84 Comparaison
Comparaison détaillée côte à côte de EPM5192GC-1 par Altera et EPM5192GI84 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GC-1 | EPM5192GI84 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,85 | $19,80 |
| Family | MAX 5000 (Classic) | MAX 5000 |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Boîtier | 100-pin Ceramic PGA (GC) | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| Type de montage | Through-Hole (PGA) | Through-Hole (PGA socket or PCB pin/peg) |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Temperature Grade | — | Industrial |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programmability | — | UV-erasable (windowed) / OTP |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| Plage de température de fonctionnement | — | -40 C to +85 C (industrial) |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |