EPM5192GC-1 vs EPM5192GM Comparaison
Comparaison détaillée côte à côte de EPM5192GC-1 par Altera et EPM5192GM par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GC-1 | EPM5192GM |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,85 | $58,00 |
| Family | MAX 5000 (Classic) | — |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | — |
| Usable Gates | 3,750 | 3,750 |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Boîtier | 100-pin Ceramic PGA (GC) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Type de montage | Through-Hole (PGA) | Through-Hole (PGA) |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial/industrial/military grade] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in ceramic PGA) |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (PLD) |
| Technology | — | CMOS |
| Number of Macrocells | — | 192 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Tension d'alimentation | — | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | — | JTAG-compatible (per MAX 5000 family) |