EPM5192JC-ES vs EPM5192GM Comparaison
Comparaison détaillée côte à côte de EPM5192JC-ES par Intel et EPM5192GM par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192JC-ES | EPM5192GM |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,45 | $58,00 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | UV Erasable Programmable Logic Device (PLD) |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| Boîtier | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Type de montage | Surface Mount | Through-Hole (PGA) |
| Technology | CMOS | CMOS |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: commercial/industrial/military grade] |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: typical VCC range] |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains lead in ceramic PGA) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Product Family | — | MAX 5000 |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | — | JTAG-compatible (per MAX 5000 family) |