EPM5192LI84 vs EPM5192GI84 Comparaison
Comparaison détaillée côte à côte de EPM5192LI84 par Altera et EPM5192GI84 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192LI84 | EPM5192GI84 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,60 | $19,80 |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| Plage de température de fonctionnement | -40 °C to +85 °C (industrial) | -40 C to +85 C (industrial) |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | — |
| Type de montage | Surface Mount (socket-compatible) | Through-Hole (PGA socket or PCB pin/peg) |
| Configuration Memory | OTP / UV-erasable EPROM | — |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| Logic Compatibility | TTL-compatible I/O | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocells | — | 192 |
| Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Boîtier | — | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Temperature Grade | — | Industrial |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programmability | — | UV-erasable (windowed) / OTP |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |