EPM7128ATC100-10 vs EPM7128AETC100-10N Comparaison
Comparaison détaillée côte à côte de EPM7128ATC100-10 par Altera et EPM7128AETC100-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteIntel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteComparaison des spécifications
| Paramètre | EPM7128ATC100-10 | EPM7128AETC100-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,95 | $9,95 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000AE |
| Architecture | Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - 2nd generation |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 2.5K | 2500 |
| User I/O Pins | 68 | — |
| Pin-to-Pin Logic Delay | 4.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Speed Grade | -10 (10 ns) | -10 |
| Core Supply Voltage | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Program Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Boîtier | 100-pin TQFP (TC100) | TQFP-100 |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Series | — | EPM7128AE |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | — | 16 |
| User I/Os | — | 84 |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | [DATA_NEEDED: maximum toggle frequency] |
| Programming | — | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Process Technology | — | CMOS EEPROM |
| PCI Compliance | — | Yes (33 MHz, -10 grade per PCI SIG 2.2) |