EPM7128ATC100-7F vs EPM7128AETI100-7 Comparaison
Comparaison détaillée côte à côte de EPM7128ATC100-7F par Altera et EPM7128AETI100-7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F NrndAltera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128ATC100-7F | EPM7128AETI100-7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $30,10 |
| Family | MAX 7000A | MAX 7000A |
| Device | EPM7128A | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Logic Array Blocks (LABs) | 8 | — |
| Usable Gates | 2.5K | 2,500 |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) | — |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) | — |
| Programmable Type | EEPROM (in-system programmable, non-volatile) | — |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | Yes (IEEE 1149.1 boundary-scan) |
| Boîtier | 100-pin TQFP (14x14 mm) | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Température de fonctionnement | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| Process Technology | CMOS, EEPROM configuration | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| Global Clock Inputs | — | 4 dedicated |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |