EPM7128SLC84-15N vs EPM7128SLI84-15 Comparaison
Comparaison détaillée côte à côte de EPM7128SLC84-15N par Altera et EPM7128SLI84-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7128SLC84-15N | EPM7128SLI84-15 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $22,21 | $8,40 |
| Device Type | Complex Programmable Logic Device (CPLD) | EE PLD (CPLD) |
| Device Family | MAX 7000 | — |
| Logic Gates | 2.5K gates | — |
| Number of Macrocells | 128 macrocells | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Speed Grade | 15 ns | — |
| Tension d'alimentation | 5 V | — |
| Number of I/Os | 68 I/Os | — |
| Boîtier | 84-pin PLCC | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Type de montage | Surface Mount | Surface Mount (PLCC socket compatible) |
| Nombre de broches | 84 pins | 84 |
| Configuration | Programmable logic device | — |
| Manufacturer | Altera Corporation | — |
| Datasheet Page Count | 66 pages | — |
| Datasheet File Size | 1 MB | — |
| Statut RoHS | Compliant | [DATA_NEEDED: rohs status] |
| Cross-Reference Note | EPM7128SLC84-15N is reported as functionally and pin-compatible with earlier EPM7128 variants in the same speed grade and package | — |
| Family | — | MAX 7000 |
| Series | — | EPM7128S |
| Macrocells | — | 128 |
| Logic Elements | — | 250 (approx.) |
| User I/O Pins | — | 84 (68 in 84-pin PLCC per some sources) |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCCINT) | — | 4.5 V to 5.5 V |
| I/O Voltage Tolerance | — | 3.3 V or 5.0 V (configurable) |
| Process Technology | — | CMOS EEPROM |
| Program Memory Type | — | EEPROM (in-system programmable) |
| Température de fonctionnement | — | -40 C to +85 C (Industrial grade, 'I' suffix) |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Maximum User Flash Endurance | — | 100 program/erase cycles |
| Data Retention | — | 20 years |