EPM7128SQC100-7 vs EPM7128SQC100-10 Comparaison
Comparaison détaillée côte à côte de EPM7128SQC100-7 par Intel et EPM7128SQC100-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128SQC100-7 | EPM7128SQC100-10 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,85 | $9,85 |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | — |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS, EEPROM-based, non-volatile | — |
| Boîtier | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Non-RoHS (legacy SnPb package) | [DATA_NEEDED: rohs_status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Gates | — | 2,500 usable gates |
| Maximum User I/O | — | 84 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Tension d'alimentation | — | 5 V |
| Process Technology | — | 5V CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG |