EPM7128SQC160-6 vs EPM7128SQI160-10 Comparaison
Comparaison détaillée côte à côte de EPM7128SQC160-6 par Altera et EPM7128SQI160-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
EPM7128SQC160-6 ObsoleteIntel
EPM7128SQI160-10 - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-160 | Intel
EPM7128SQI160-10 ObsoleteComparaison des spécifications
| Paramètre | EPM7128SQC160-6 | EPM7128SQI160-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,10 | $19,95 |
| Series | MAX 7000S | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2500 | — |
| User I/O Pins | 100 | 100 (approx., PQFP-160) |
| Logic Array Blocks (LABs) | 4 | — |
| Pin-to-Pin Propagation Delay (tPD) | 6 ns | — |
| Maximum Internal Frequency (fMAX) | 147.1 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | — |
| Process Technology | 0.5 µm CMOS EEPROM | CMOS, EEPROM-based configuration |
| Programmable Type | In-System Programmable (ISP) via JTAG | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Boîtier | 160-Pin PQFP (28 × 28 mm) | PQFP-160 (Plastic Quad Flat Pack) |
| Type de montage | Surface Mount | Surface Mount |
| Supplier Device Package | 160-PQFP (28×28) | — |
| JTAG Support | Yes (IEEE Std 1149.1) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status — Altera MAX 7000S family was originally lead-based; lead-free variants exist with -N suffix] | [DATA_NEEDED: rohs_status] |
| Niveau MSL | [DATA_NEEDED: MSL rating not in verified data] | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Elements / Gates | — | 2.5K equivalent gates |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 100 MHz |
| Logic Blocks (LABs) | — | 4 (16 macrocells each) |
| Supply Voltage VCCINT | — | 5 V |
| I/O Voltage Tolerance | — | 3.3 V / 5 V multi-volt interface |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |