EPM7160EQC100-20 vs EPM7160ELC84-20 Comparaison
Comparaison détaillée côte à côte de EPM7160EQC100-20 par Altera et EPM7160ELC84-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP
EPM7160EQC100-20 ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EPM7160EQC100-20 | EPM7160ELC84-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,10 | $16,95 |
| Series | MAX 7000 | — |
| Family | MAX 7000 CPLD | MAX 7000 |
| Architecture | CMOS EEPROM-based, non-volatile | Second-generation MAX |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | — |
| I/O Voltage Support | 3.3 V or 5 V configurable | — |
| Boîtier | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Type de montage | Surface Mount | Surface Mount (PLCC socket compatible) |
| Température de fonctionnement | 0 °C to +90 °C (commercial) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | — |
| Reprogram Cycles (typical) | 100 | — |
| Statut RoHS | Not RoHS compliant (legacy Altera MAX 7000) | [DATA_NEEDED: RoHS compliance per specific part marking] |
| Logic Elements per Macrocell | 36 product terms (expandable) | — |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | — | Yes (5.0-V ISP) |
| Technology | — | CMOS EEPROM |
| Global Clock Inputs | — | 4 |
| Logic Element Type | — | EEPROM-based macrocell |