EPM7160SLC84-10N vs EPM7160STI100-10N Comparaison
Comparaison détaillée côte à côte de EPM7160SLC84-10N par Intel et EPM7160STI100-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
EPM7160STI100-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM7160SLC84-10N | EPM7160STI100-10N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $7,80 |
| Family | MAX 7000S | MAX 7000S |
| Logic Elements / Macrocells | 160 macrocells | — |
| Usable Gates | 3,200 gates | 3200 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 (also reported as 60 or 36 depending on variant) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Speed (fCNT) | up to 175.4 MHz | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage - Core (VCC) | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programming | Yes, via IEEE Std. 1149.1 JTAG | — |
| Program / Erase Cycles | 100 minimum | — |
| Data Retention | 20 years minimum | — |
| Boîtier | 84-pin PLCC (J-lead, surface mount) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| Lead-Free / RoHS | Yes (-N suffix indicates lead-free) | Yes (lead-free per 'I' industrial suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 160 |
| User I/Os | — | 84 (per Mouser listing; up to 104 per alternate datasheets) |
| Logic Blocks | — | 10 (LABs) |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency | — | 100 MHz |
| Supply Voltage VCC | — | 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG/IEEE 1149.1, 5.0V ISP) |
| Température de fonctionnement | — | -40C to +85C (industrial, 'I' suffix) |
| Package Type | — | 100-pin TQFP (TQFP-100) |
| Process Technology | — | CMOS, EEPROM-based |