EPM7160SQC160-7 vs EPM7160SQC160-10N Comparaison
Comparaison détaillée côte à côte de EPM7160SQC160-7 par Altera et EPM7160SQC160-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7160SQC160-7 | EPM7160SQC160-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $8,10 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Température de fonctionnement | 0 °C to 70 °C (commercial) | 0 C to 70 C (Commercial) |
| Boîtier | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (SQC) 31.2 x 31.2 mm |
| Type de montage | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Statut RoHS | Not Compliant (per Arrow listing) | Non-Compliant (Pb-bearing PQFP) |
| Part Status | Obsolete | — |
| Macro Cells | — | 160 |
| Usable Gates | — | 3,200 |
| Logic Elements / Blocks | — | 10 Logic Array Blocks (LABs) |
| User I/O Pins | — | 104 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 167 MHz |
| Counter Speed (fCNT) | — | 100 MHz |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Memory Technology | — | EEPROM |