EPM7160STI100-10 vs EPM7160STC100-10F Comparaison
Comparaison détaillée côte à côte de EPM7160STI100-10 par Altera et EPM7160STC100-10F par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7160STI100-10 | EPM7160STC100-10F |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $90,43 | $9,95 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3,200 |
| User I/Os | 84 | — |
| Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Operating Frequency | 100 MHz | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Température de fonctionnement | -40 C to +85 C (Industrial) | 0 °C to +70 °C (commercial) |
| Boîtier | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP (1.0 mm height, lead-free) |
| Type de montage | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] | Lead-free (suffix F indicates Pb-free) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 84 |
| Dedicated Inputs | — | 4 |
| Maximum Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Process Technology | — | CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |