EPM7192SQC160-10 vs EPM7192EGM160-20 Comparaison
Comparaison détaillée côte à côte de EPM7192SQC160-10 par Altera et EPM7192EGM160-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndAltera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteComparaison des spécifications
| Paramètre | EPM7192SQC160-10 | EPM7192EGM160-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,25 | $15,60 |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | 12 |
| User I/Os | 124 | — |
| Usable Gates | 3750 | 600 to 5,000 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Boîtier | PQFP-160 (SQC) 28x28 mm | PGA-160 (160-pin Pin Grid Array) |
| Pin/Package Type | Surface Mount, Gull-Wing | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Device Type | — | EE CMOS CPLD (Electrically Erasable) |
| Maximum User I/O Pins | — | 120 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Counter Frequency (max) | — | 175.4 MHz |
| I/O Standards | — | 3.3 V or 5 V configurable |
| Global Clock Inputs | — | 2 (GCLK1, GCLK2) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| Température de fonctionnement | — | -40C to +125C (industrial) |
| Technology Node | — | CMOS, second-generation MAX architecture |