EPM7192SQC160-10 vs EPM7192EQC160-20 Comparaison
Comparaison détaillée côte à côte de EPM7192SQC160-10 par Altera et EPM7192EQC160-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndIntel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteComparaison des spécifications
| Paramètre | EPM7192SQC160-10 | EPM7192EQC160-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,25 | $58,26 |
| Family | MAX 7000S | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 124 | — |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Boîtier | PQFP-160 (SQC) 28x28 mm | — |
| Pin/Package Type | Surface Mount, Gull-Wing | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Series | — | MAX 7000 |
| Programmable Type | — | EE PLD (EEPROM-based) |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of User I/O Pins | — | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | — | 20 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz typical |
| Température de fonctionnement | — | -40C to +85C (industrial) |
| Boîtier / Format | — | 160-BQFP / 160-PQFP (28x28 mm) |
| Type de montage | — | Surface Mount |
| In-System Programmable (ISP) | — | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | — | Yes |
| Power-Saving Mode | — | Yes, programmable per macrocell |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |