EPM7256AETC100-10N vs EPM7256AETC100-5C Comparaison
Comparaison détaillée côte à côte de EPM7256AETC100-10N par Altera et EPM7256AETC100-5C par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N ObsoleteAltera
EPM7256AETC100-5C - MAX 7000 CPLD, 256 Macrocells, 84 I/O, TQFP-100 | Altera
EPM7256AETC100-5C ObsoleteComparaison des spécifications
| Paramètre | EPM7256AETC100-10N | EPM7256AETC100-5C |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,10 | $48,90 |
| Family | MAX 7000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | — |
| Maximum User I/Os | 84 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) | — |
| Boîtier | 100-pin TQFP | TQFP-100 |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] | — |
| Process Technology | 0.30 µm EEPROM | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Statut RoHS | [DATA_NEEDED: not confirmed in provided data] | Non-compliant (Pb-bearing TQFP package) |
| Lead-Free / Pb-Free | [DATA_NEEDED: not confirmed in provided data] | — |
| Product Family | — | MAX 7000A |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 84 |
| Usable Gates (typical) | — | 6400 |
| Propagation Delay (tPD) | — | 5 ns |
| Maximum Counter Frequency (fCNT) | — | 200 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V compatible |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |
| Température de fonctionnement | — | 0 °C to +70 °C (commercial) |
| Lead-Free | — | No |