EPM7256SQC208-15 vs EPM7256SRI208-10 Comparaison
Comparaison détaillée côte à côte de EPM7256SQC208-15 par Altera et EPM7256SRI208-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7256SQC208-15 | EPM7256SRI208-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,65 | $27,20 |
| Family | MAX 7000S | — |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | 5,000 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Plage de température de fonctionnement | 0 C to +70 C (Commercial) | Industrial (-40C to +85C) |
| Boîtier | 208-pin PQFP (28x28 mm) | 208-pin RQFP (PowerQuad) |
| Type de montage | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Statut RoHS | Contains lead / RoHS non-compliant (per third-party listing) | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Contains lead | — |
| Logic Family | — | MAX 7000S (EEPROM-based CPLD) |
| Logic Array Blocks | — | 16 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 100 MHz |
| Supply Voltage (Internal) | — | 4.5 V to 5.5 V |
| Logic Family Technology | — | CMOS |
| Programmable Type | — | In-System Programmable (ISP) via JTAG |
| JTAG Boundary Scan | — | Yes (BST circuitry) |
| Packaging | — | Tray |