EPM9320LC84-15 vs EPM9320LC84-20 Comparaison
Comparaison détaillée côte à côte de EPM9320LC84-15 par Intel et EPM9320LC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320LC84-15 | EPM9320LC84-20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,95 | $9,75 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | 16 ns |
| Fréquence d'horloge maximale | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Boîtier | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier) |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to 70 C |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Statut RoHS | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Internal Counter Frequency | — | 118 MHz |
| Tension d'alimentation | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |