EPM9320LC84-20 vs EPM9320ALC84-10 Comparaison
Comparaison détaillée côte à côte de EPM9320LC84-20 par Altera et EPM9320ALC84-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320LC84-20 | EPM9320ALC84-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $19,80 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Boîtier | PLCC-84 (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-Lead) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Counter Frequency | 118 MHz | — |
| Tension d'alimentation | 5.0 V | — |
| Température de fonctionnement | 0 C to 70 C | [DATA_NEEDED: commercial/industrial grade] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| Dedicated Inputs | 4 (global clock / clear / OE) | 16 |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | MAX (Multiple Array MatriX) with FastTrack Interconnect |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 52 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| Type de montage | — | Surface Mount / Through-Hole (PLCC socket) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |