EPM9400LC84-20 vs EPM9320LC84-15 Comparaison
Comparaison détaillée côte à côte de EPM9400LC84-20 par Altera et EPM9320LC84-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9400LC84-20 | EPM9320LC84-15 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $38,50 | $17,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | — |
| Macrocells | 400 | 320 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | 6,000 |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Boîtier | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | CMOS EEPROM | — |
| Température de fonctionnement | Commercial (0C to +70C) - assumed from -20 speed grade | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Type de montage | Surface Mount (PLCC socket or SMT land pattern) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 20 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Fréquence d'horloge maximale | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |