EPM9400RC208-20 vs EPM9320RI208-20N Comparaison
Comparaison détaillée côte à côte de EPM9400RC208-20 par Altera et EPM9320RI208-20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9400RC208-20 | EPM9320RI208-20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $60,49 | $0,00 |
| Family | MAX 9000 | — |
| Programmable Type | In System Programmable (ISP) | — |
| Macro Cells | 400 | — |
| Usable Gates | 8,000 | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | — |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| JTAG Interface | IEEE Std. 1149.1 | IEEE Std. 1149.1 compliant |
| Boîtier | 208-pin RQFP (28x28 mm) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Supplier Device Package | 208-RQFP | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Speed Grade | -20 (20 ns) | — |
| Device Family | — | MAX 9000 (EPM9320) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| Plage de température de fonctionnement | — | -40C to +85C (Industrial) |
| In-System Programmability | — | Yes, 5.0 V ISP via JTAG |
| Configuration Memory | — | EEPROM (non-volatile) |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |