EPM9560GC280-15N vs EPM9560GI280-20 Comparaison
Comparaison détaillée côte à côte de EPM9560GC280-15N par Intel et EPM9560GI280-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560GC280-15N | EPM9560GI280-20 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $125,00 | $162,50 |
| Device Family | MAX 9000 | MAX 9000 |
| Product Type | EE PLD / CPLD | — |
| Macrocell Count | 560 | — |
| Usable Gates | 12,000 (typical) | 12,000 |
| Propagation Delay (tPD) | 16.6 ns | — |
| Fréquence d'horloge maximale | 117.6 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Maximum Supply Voltage | 5.25 V | — |
| Logic Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | — |
| Boîtier | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin PGA (PIN/PEG, square) |
| Package Code | PGA / CPGA280 | PGA |
| Terminal Form | PIN/PEG | PIN/PEG (through-hole PGA) |
| Operating Temperature Grade | Commercial | — |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Maximum User I/O Pins | — | 216 |
| Flip-Flops | — | 772 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programming Technology | — | EEPROM (non-volatile) |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |
| Statut RoHS | — | [DATA_NEEDED: RoHS status for GI PGA package] |