EPM9560GM280-15 vs EPM9560GI280-20 Comparaison
Comparaison détaillée côte à côte de EPM9560GM280-15 par Altera et EPM9560GI280-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560GM280-15 | EPM9560GI280-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $110,00 | $162,50 |
| Family | MAX 9000 | — |
| Device Type | EE PLD (EEPROM-based) | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | 772 |
| User I/O | 216 | — |
| Logic Array Blocks (LABs) | 35 (16 macrocells each) | 28 (16 macrocells each) |
| Supply Voltage (Nominal) | 5.0 V | — |
| Supply Voltage (Max) | 5.5 V | — |
| I/O Logic Level Support | 3.3 V or 5 V | — |
| Pin-to-Pin Delay (tPD) | 15 ns (speed grade -15) | — |
| Boîtier | FineLine BGA-280 (GM) | 280-pin PGA (PIN/PEG, square) |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5V ISP via JTAG IEEE 1149.1) | Yes (IEEE Std. 1149.1 JTAG) |
| Température de fonctionnement | -40C to +85C (industrial) | — |
| Statut RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status for GI PGA package] |
| Niveau MSL | 3 (168 Hours) | — |
| Device Family | — | MAX 9000 |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Usable Gates | — | 12,000 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |