EPM9560RC208-10 vs EPM9560RC208-15C Comparaison
Comparaison détaillée côte à côte de EPM9560RC208-10 par Intel et EPM9560RC208-15C par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RC208-10 | EPM9560RC208-15C |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,40 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based CPLD (EPLD) |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 (208-pin package variant) | — |
| Usable Gates | 12,000 | 12,000 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: internal toggle frequency in MHz] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standards Supported | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) | — |
| Configuration Memory | EEPROM (in-system programmable via JTAG) | EEPROM (non-volatile) |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Température de fonctionnement | 0C to +70C (commercial) | — |
| Boîtier | 208-pin RQFP (Plastic Quad Flat Pack) | 208-pin RQFP |
| Type de montage | Surface Mount | Surface Mount |
| Lead-Free | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] | — |
| Statut RoHS | [DATA_NEEDED: not stated in retrieved distributor listings] | [DATA_NEEDED: RoHS status] |
| Programmability | JTAG (IEEE 1149.1) in-system programming | — |
| User I/O Pins | — | 149 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Counter Frequency | — | 117.6 MHz |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Plage de température de fonctionnement | — | 0C to +70C (commercial) |
| Speed Grade | — | -15 (15 ns) |
| Logic Architecture | — | Multiple Array MatriX (MAX) third generation |