EPM9560RC240-15 vs EPM9560RC240-15N Comparaison
Comparaison détaillée côte à côte de EPM9560RC240-15 par Intel et EPM9560RC240-15N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RC240-15 | EPM9560RC240-15N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $174,72 | $27,85 |
| Logic Family | MAX 9000 (CMOS EEPROM-based) | CMOS (EEPROM-based) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 191 | — |
| Boîtier | 240-pin RQFP (32x32 mm) with exposed pad | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Maximum Internal Frequency | 145 MHz | — |
| Tension d'alimentation | 5.0 V | 5.0 V |
| Température de fonctionnement | 0 C to 70 C (commercial) | 0C to +70C (Commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Number of Terminals | 240 | — |
| Package Code | FQFP / RQFP | — |
| Terminal Form | Gull Wing | — |
| Package Shape | Square | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | MAX 9000 |
| Family | — | MAX 9000 (third-generation Multiple Array MatriX) |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |