EPM9560RC240-3 vs EPM9560RC240-1O Comparaison
Comparaison détaillée côte à côte de EPM9560RC240-3 par Altera et EPM9560RC240-1O par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM9560RC240-3 | EPM9560RC240-1O |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $202,32 | $51,07 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 |
| Usable Gates | 12000 | 12,000 |
| Logic Array Blocks (LABs) | 20 | 35 |
| Pin-to-Pin Propagation Delay | 3 ns (speed grade -3) | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Supply Voltage (VCCIO) | 5 V | — |
| User I/O Pins | 192 | — |
| Boîtier | 240-pin RQFP (PowerQuad II) | RQFP-240 (240-pin Reduced-height QFP) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Plage de température de fonctionnement | 0C to +70C (commercial) | — |
| Statut RoHS | [DATA_NEEDED: RoHS] | Compliant (per Altera/Intel product page) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Niveau MSL | [DATA_NEEDED: MSL] | — |
| JTAG Support | [DATA_NEEDED: JTAG] | — |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | — | 3.0 ns |
| Clock-to-Output (tFCO) | — | 4.8 ns |
| Maximum Internal Frequency (fCNT) | — | 145 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Grade) | — | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | — | CMOS EEPROM, 0.65 um |
| Programming | — | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array MatriX (MAX), third generation |
| Lead-Free | — | Yes |