EPM9560RI304 vs EPM9560RC304-15C Comparaison
Comparaison détaillée côte à côte de EPM9560RI304 par Altera et EPM9560RC304-15C par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteComparaison des spécifications
| Paramètre | EPM9560RI304 | EPM9560RC304-15C |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $24,50 |
| Device Family | MAX 9000 | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Maximum User I/O Pins | 216 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE 1149.1 JTAG) |
| JTAG Interface | IEEE Std. 1149.1 (JTAG) | — |
| Boîtier | 304-pin BFQFP/RQFP (HFQFP) | 304-pin RQFP |
| Package Code | HFQFP, square | — |
| Terminal Form | Gull wing | — |
| Number of Terminals | 304 | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Type de montage | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array | Multiple Array MatriX (MAX), 3rd generation |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Tension d'alimentation | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Program/Erase Endurance | — | 100 cycles minimum |
| Température de fonctionnement | — | 0 C to +70 C (Commercial) |