LTC2150CUJ-14 vs LTC2256CUJ-14 Comparaison
Comparaison détaillée côte à côte de LTC2150CUJ-14 par Analog Devices et LTC2256CUJ-14 par Analog Devices. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ ActifComparaison des spécifications
| Paramètre | LTC2150CUJ-14 | LTC2256CUJ-14 |
|---|---|---|
| Marque | Analog Devices | Analog Devices |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $41,58 | $6,90 |
| Résolution | 14 bit | 14 bit |
| Number of Channels | 1 | — |
| Sample Rate | 170 Msps | 25 Msps |
| Architecture | Pipelined | Pipelined |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | — |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | — |
| INL (typical) | ±0.85 LSB | — |
| DNL (typical) | ±0.25 LSB | — |
| Transition Noise | 1.82 LSBRMS | 1.13 LSB RMS |
| Missing Codes | None over temperature | — |
| Full-Power Sample/Hold Bandwidth | 1.25 GHz | — |
| Digital Output Interface | DDR LVDS | — |
| Encode Clock Inputs | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) | — |
| Clock Duty-Cycle Stabilizer | Optional (selectable) | — |
| Configuration Interface | Serial SPI port | Serial SPI port |
| Latency | 5 clock cycles | — |
| Power-Saving Modes | Sleep and Nap modes | Nap mode, full shutdown |
| Boîtier | 40-QFN (6 mm × 6 mm) with exposed pad | 40-QFN (6 mm x 6 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant (Pb-free #PBF suffix) | Compliant (PBF suffix) |
| Number of Inputs | — | 1 |
| Tension d'alimentation | — | 1.8 V (single) |
| Power Dissipation | — | 35 mW at 25 Msps |
| INL | — | ±1 LSB (typical) |
| DNL | — | ±0.3 LSB (typical) |
| SNR | — | 73 dB |
| Input Bandwidth (Full Power) | — | 800 MHz |
| Input Range | — | 1 Vp-p to 2 Vp-p (selectable, differential) |
| Digital Output Modes | — | Full-rate CMOS, DDR CMOS, DDR LVDS (selectable) |
| Output Supply Range (CMOS) | — | 1.2 V to 1.8 V |
| Pin/Package Code | — | UJ (QFN-40, 6x6 mm) |
| Optional Features | — | Clock duty-cycle stabilizer, data output randomizer |
| Température de fonctionnement | — | 0C to +70C (commercial C-grade) |