MSC8156ESVT1000B vs MSC8156ESAG1000B Comparaison
Comparaison détaillée côte à côte de MSC8156ESVT1000B par NXP Semiconductors et MSC8156ESAG1000B par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
MSC8156ESVT1000B - 6-Core SC3850 DSP @ 1GHz | NXP | FCBGA-783
MSC8156ESVT1000B ObsoleteNXP Semiconductors
MSC8156ESAG1000B - 6x SC3850 1GHz DSP SoC | NXP Semiconductors
MSC8156ESAG1000B ✗ Fin de vieComparaison des spécifications
| Paramètre | MSC8156ESVT1000B | MSC8156ESAG1000B |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | DSP | DSP |
| Statut du cycle de vie | Obsolete | Fin de vie |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $138,00 | $112,00 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | StarCore | — |
| Type | SC3850 Six Core DSP | — |
| Number of Cores | 6 | — |
| Core Architecture | StarCore SC3850 | — |
| Clock Rate | 1 GHz | — |
| On-Chip RAM | 576 KB | — |
| Non-Volatile Memory | ROM 96 KB | — |
| L1 Instruction Cache (per core) | 32 KB | — |
| L1 Data Cache (per core) | 32 KB | — |
| Unified L2 Cache | 512 KB | — |
| Voltage - I/O | 2.50 V | — |
| Voltage - Core | 1.00 V | — |
| Interface | Ethernet, I2C, PCI, RGMII, Serial RapidIO, SGMII, SPI, UART/USART | — |
| Boîtier | 783-BBGA, FCBGA | 783-ball FCBGA (29x29 mm) |
| Packaging | Tray | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +105C |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| DSP Cores | — | 6x SC3850 StarCore cores |
| Core Clock Frequency | — | 1 GHz per core |
| Aggregate Performance | — | [DATA_NEEDED: aggregate MMACS rating] |
| Process Technology | — | 45 nm CMOS |
| Hardware Accelerator | — | MAPLE-B baseband accelerator (turbo decode) |
| Memory Controller | — | 64-bit DDR2/DDR3, up to 800 MT/s |
| SerDes Lanes | — | 2 lanes, SRIO or PCIe (selectable) |
| Ethernet | — | 1x Gigabit Ethernet MAC |
| Packet Engine | — | QUICC Engine subsystem |
| Security Engine | — | SEC 4.0 (Cryptographic accelerator) |
| Tension d'alimentation | — | [DATA_NEEDED: core and I/O rail voltages] |
| Statut du cycle de vie | — | End of Life (per NXP PCN) |