MSC8157ETAG1000A vs MSC8157TAG1000A Comparaison
Comparaison détaillée côte à côte de MSC8157ETAG1000A par NXP Semiconductors et MSC8157TAG1000A par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
MSC8157ETAG1000A - SC3850 Six-Core DSP 1GHz | NXP Semiconductors
MSC8157ETAG1000A NrndNXP Semiconductors
MSC8157TAG1000A - 6-Core SC3850 DSP, 1GHz, MAPLE-B2 | NXP
MSC8157TAG1000A ⚠ Dernier achatComparaison des spécifications
| Paramètre | MSC8157ETAG1000A | MSC8157TAG1000A |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | DSP | DSP |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $224,50 | $178,00 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | StarCore MSC815x | — |
| Core Architecture | SC3850 (six-core) | — |
| Number of Cores | 6 | — |
| Core Clock Frequency | 1 GHz | — |
| Aggregate Throughput | >24 GMACS (16-bit fixed point) | — |
| Per-Core MMACS | 4000 MMACS @ 16-bit, 2000 MMACS @ 32-bit | — |
| Accelerator Engine | MAPLE-B baseband coprocessor (Turbo/Viterbi) | — |
| Memory Controllers | Dual DDR2/DDR3 with ECC | — |
| High-Speed I/O | 4x Serial RapidIO, 2x GbE SGMII, PCIe Gen 2 | — |
| Boîtier | 783-FCBGA (29x29 mm) | 783-FCPBGA (29x29 mm) |
| Type de montage | Surface Mount (BGA) | — |
| Température de fonctionnement | -40C to +105C | -40C to +105C |
| Supply Voltages | 1.0 V core, 1.5 V DDR, 3.3 V I/O | — |
| Niveau MSL | 4 (per JEDEC J-STD-020 for large FCBGA) | [DATA_NEEDED] |
| Statut RoHS | Compliant | [DATA_NEEDED] |
| Lead-Free | Yes | — |
| Process Node | [DATA_NEEDED: process node] | — |
| Device Type | — | Six-core Digital Signal Processor (DSP) |
| DSP Architecture | — | StarCore SC3850 (6x cores) |
| Core Frequency | — | 1 GHz per core |
| L1 Instruction Cache | — | 32 KB per core |
| L1 Data Cache | — | 32 KB per core |
| Unified L2 Cache | — | 512 KB (configurable as M2 in 64 KB increments) |
| Accelerator | — | MAPLE-B2 baseband accelerator |
| Memory Controller | — | Dual-channel DDR2/DDR3 with ECC |
| High-Speed Serial I/O | — | 2x SRIO, 2x PCIe, 2x GbE, 2x CIPRI |
| Ball Pitch | — | 1.0 mm |
| Tension d'alimentation | — | [DATA_NEEDED: core/IO voltage] |
| MMU | — | Yes |
| Interrupt Controller | — | EPIC (Extended Programmable Interrupt Controller) |
| Timers | — | 2x 32-bit general-purpose per core |