P5010NXN1QMB557 vs P5010NSN1QMB Comparaison
Comparaison détaillée côte à côte de P5010NXN1QMB557 par NXP Semiconductors et P5010NSN1QMB par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
P5010NXN1QMB557 - QorIQ P5 2GHz 64-Bit MPU | NXP 1295-FCPBGA
P5010NXN1QMB557 ✓ ActifNXP Semiconductors
P5010NSN1QMB - QorIQ P5010 SoC, 64-bit Power Arch, 2.0GHz, 1295-FCBGA | NXP
P5010NSN1QMB ✓ ActifComparaison des spécifications
| Paramètre | P5010NXN1QMB557 | P5010NSN1QMB |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $129,60 | $318,25 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Architecture | PowerPC e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 2.0 GHz | 2.0 GHz |
| External Data Bus Width | 64-bit | — |
| Address Bus Width | 16-bit (per Microchip USA listing) | — |
| Boîtier | 1295-ball FCPBGA (37.5 x 37.5 mm) | 1295-FCBGA (37.5 x 37.5 mm) |
| Ball Pitch | 1.00 mm | — |
| JESD-30 Package Code | S-PBGA-B1295 | — |
| Process Technology | CMOS | — |
| Integrated Cache | Yes (L1 + L2) | — |
| Low-Power Mode Support | Yes | — |
| Statut RoHS | Compliant | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +105C |
| Type de montage | Surface Mount (BGA) | — |
| Architecture | — | Power Architecture e5500 (64-bit) |
| Core Count | — | 1 core |
| Cache (L1 Instruction per core) | — | 32 KB |
| Cache (L1 Data per core) | — | 32 KB |
| Cache (L2 shared frontside) | — | 1 MB |
| Memory Controller | — | DDR3 with ECC support |
| PCIe | — | PCI Express Gen 2 controllers integrated |
| Ethernet | — | Dual Gigabit Ethernet |
| High-Speed Interconnect | — | Serial RapidIO (SRIO) |
| Hardware Acceleration | — | DPAA (Data Path Acceleration Architecture) engine |
| Security Engine | — | SEC crypto engine integrated |
| Encryption | — | Hardware-accelerated |