RTAX2000S-CGS624V vs RTAX2000S-CG624PROTO Comparaison
Comparaison détaillée côte à côte de RTAX2000S-CGS624V par Microchip Technology et RTAX2000S-CG624PROTO par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ ActifMicrochip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ ActifComparaison des spécifications
| Paramètre | RTAX2000S-CGS624V | RTAX2000S-CG624PROTO |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $0,00 |
| Equivalent System Gates | 2000000 | — |
| Configurable Logic Blocks (CLBs) | 21504 | — |
| Logic Cells | 32256 | — |
| Technology | Digital CMOS, anti-fuse OTP | — |
| Core Supply Voltage (Nominal) | 1.5 V | — |
| Core Supply Voltage Range | 1.425 V to 1.575 V | — |
| Température de fonctionnement | -55C to +125C | -55C to +125C |
| Boîtier | CG624 ceramic column grid array | CCGA-624 (ceramic column grid array, 624 balls) |
| Type de montage | Surface Mount | Surface Mount |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S Radiation-Tolerant FPGA |
| Configuration Type | One-Time Programmable (anti-fuse), live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM blocks (FIFO / dual-port capable) |
| Clocking | Segmentable clocks | — |
| Routing Features | Chip-wide highway routing, carry logic | — |
| Application Domain | Space-flight systems | — |
| Max Family Density | 4000000 equivalent system gates (family max) | — |
| System Gates | — | 2,000,000 |
| Logic Cells (R-cells) | — | 21,504 |
| D-Flip-Flops (Registers) | — | 32,256 |
| Logic Architecture | — | CMOS antifuse (OTP), SEU-hardened |
| Logic Family | — | CMOS |
| Configuration | — | Live at power-up (non-volatile antifuse) |
| SEU Immunity | — | SEU rate < 10^-10 errors/bit-day (per family datasheet) |
| Prototyping Variant | — | Yes (PROTO suffix) |
| I/O Standards | — | Single-ended and differential (P/N pin pairs) |
| Design Software | — | Microsemi/Microchip Libero SoC |
| Tension d'alimentation | — | [DATA_NEEDED: core and I/O supply voltage] |
| Total Ionizing Dose (TID) | — | [DATA_NEEDED: TID rating in krad(Si)] |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Maximum I/O Count (624-ball pkg) | — | [DATA_NEEDED: user I/O count] |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |