RTAX2000SL-1LG624V vs RTAX2000S-1LG624V Comparaison
Comparaison détaillée côte à côte de RTAX2000SL-1LG624V par Microchip Technology et RTAX2000S-1LG624V par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX2000SL-1LG624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-1LG624V ✓ ActifMicrochip Technology
RTAX2000S-1LG624V - 2M-Gate Rad-Tolerant Antifuse FPGA | Microchip
RTAX2000S-1LG624V ✓ ActifComparaison des spécifications
| Paramètre | RTAX2000SL-1LG624V | RTAX2000S-1LG624V |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9 600,00 | $0,00 |
| Logic Cells | 32256 | — |
| CLBs (Configurable Logic Blocks) | 21504 | — |
| Equivalent Gates | 2000000 (approx.) | — |
| Family | RTAX-S/SL (radiation-tolerant FPGA) | — |
| Process Variant | SL (super low-power) CMOS | — |
| Core Supply Voltage | 1.5 V (nominal) | [DATA_NEEDED: core supply voltage] |
| Température de fonctionnement | -55C to +125C | — |
| Boîtier | 624-terminal ceramic CGA (CG624) | CG624, 624-pin ceramic column grid array |
| Type de montage | Surface Mount (column grid array) | Surface Mount |
| Programming Technology | Anti-fuse, one-time programmable | One-time programmable antifuse, nonvolatile |
| Configuration | Live at power-up, single-chip (no external config storage) | Single-chip, live at power-up (no boot device required) |
| Radiation Tolerance | Radiation-tolerant for space flight systems | — |
| Speed Grade | -1 | -1 |
| Application Class | Space flight / aerospace | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Embedded Memory | [DATA_NEEDED: embedded SRAM bits] | Up to 540 kbits SRAM with optional EDAC protection |
| Equivalent System Gates | — | 2,000,000 gates |
| Configurable Logic Blocks (CLBs) | — | 21,504 |
| User I/Os (maximum, family) | — | Up to 684 |
| Total Ionizing Dose (TID), functional | — | 300 krad (Si) |
| Total Ionizing Dose (TID), parametric | — | 200 krad (Si) |
| SEU Immunity | — | Less than 1E-10 errors per bit-day |
| Process Technology | — | Digital CMOS |
| Package Temperature Suffix | — | V (space/military screening variant) |
| Family Lineage | — | RTAX-S/SL, based on commercial Axcelerator family |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |