RTAX250S-1CG624E vs RTAX250SL-1CG624E Comparaison
Comparaison détaillée côte à côte de RTAX250S-1CG624E par Microchip Technology et RTAX250SL-1CG624E par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250S-1CG624E - 250K-Gate Rad-Tolerant FPGA 624-CCGA | Microchip
RTAX250S-1CG624E ✓ ActifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ ActifComparaison des spécifications
| Paramètre | RTAX250S-1CG624E | RTAX250SL-1CG624E |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $960,00 | $1,00 |
| Family | RTAX-S Radiation-Tolerant FPGA | — |
| Equivalent System Gates | 250,000 | 250,000 gates |
| Logic Cells | 2816 | 4224 |
| Maximum Toggle Frequency | 649 MHz | — |
| CLB Combinatorial Delay (Max) | 0.930 ns | — |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Process Technology | 0.15 um CMOS antifuse | 0.15 um CMOS |
| Speed Grade | -1 (approximately 15% faster than standard) | — |
| Boîtier | 624-pin Ceramic Column Grid Array (CCGA) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Température de fonctionnement | -55C to +125C | -55C to +125C |
| Configuration Type | One-time programmable antifuse, live at power-up | — |
| Logic Family | CMOS | CMOS |
| SEU Hardening | SEU-hardened registers, immune to single-event upsets | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control | Embedded SRAM with built-in FIFO control logic |
| Type de montage | Surface Mount | Surface Mount (ceramic column grid array) |
| Application Domain | Space flight / satellite systems | — |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Radiation Tolerance | — | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |