RTAX250SL-1CG624V vs RTAX250SL-1CG624E Comparaison
Comparaison détaillée côte à côte de RTAX250SL-1CG624V par Microchip Technology et RTAX250SL-1CG624E par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250SL-1CG624V - 250k-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1CG624V ✓ ActifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ ActifComparaison des spécifications
| Paramètre | RTAX250SL-1CG624V | RTAX250SL-1CG624E |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $1,00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Equivalent Gates | 250000 gates | — |
| Logic Cells | 4224 | 4224 |
| CLBs | 2816 | — |
| User I/O Inputs | 248 | — |
| User I/O Outputs | 248 | — |
| Core Supply Voltage | 1.425 V to 1.575 V | 1.5 V (1.425 V to 1.575 V) |
| Technology | CMOS, antifuse | — |
| Configuration | Live at power-up, single-chip | Live-at-power-up, true single-chip operation |
| Speed Grade | -1 | — |
| Boîtier | 624-pin ceramic column grid array (CGA) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Type de montage | Surface Mount | Surface Mount (ceramic column grid array) |
| Radiation Tolerance | Radiation-tolerant (space-flight) | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Plage de température de fonctionnement | [DATA_NEEDED: Operating Temperature Range] | — |
| SEU Characterization | SEU-optimized SL fabric generation | — |
| Statut RoHS | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: RoHS status] |
| Equivalent System Gates | — | 250,000 gates |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Process Technology | — | 0.15 um CMOS |
| Logic Family | — | CMOS |
| Température de fonctionnement | — | -55C to +125C |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Embedded Memory | — | Embedded SRAM with built-in FIFO control logic |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |