RTAX250SL-1LG624V vs RTAX250SL-1CG624E Comparaison
Comparaison détaillée côte à côte de RTAX250SL-1LG624V par Microchip Technology et RTAX250SL-1CG624E par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250SL-1LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1LG624V ✓ ActifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ ActifComparaison des spécifications
| Paramètre | RTAX250SL-1LG624V | RTAX250SL-1CG624E |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $950,00 | $1,00 |
| Equivalent System Gates | 250,000 gates | 250,000 gates |
| Logic Cells | 4224 | 4224 |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Architecture | CMOS antifuse (Axcelerator-derived) | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Core Supply Voltage | 1.5 V nominal | 1.5 V (1.425 V to 1.575 V) |
| Speed Grade | -1 | — |
| Boîtier | 624-terminal ceramic CGA (LG624), 1.270 mm terminal pitch | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Type de montage | Surface Mount | Surface Mount (ceramic column grid array) |
| Température de fonctionnement | -55C to +125C | -55C to +125C |
| Configuration Type | One-Time Programmable (antifuse) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clock Resources | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Dedicated carry logic | — |
| Application Domain | Space-flight systems | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Total Ionizing Dose Tolerance | [DATA_NEEDED: TID level] | — |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Process Technology | — | 0.15 um CMOS |
| Logic Family | — | CMOS |
| Radiation Tolerance | — | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |