XC3090L-8PCG84C vs XC3090L-8PCG84I Comparaison
Comparaison détaillée côte à côte de XC3090L-8PCG84C par Xilinx et XC3090L-8PCG84I par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-8PCG84C | XC3090L-8PCG84I |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $26,10 | $61,75 |
| Family | XC3000A/L Series FPGA | XC3000L Low-Voltage Field Programmable Gate Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | 70 |
| Boîtier | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (PCG84) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | — |
| Speed Grade | -8 (moderate) | -8 |
| Température de fonctionnement | 0 C to +70 C (commercial 'C' suffix) | -40 °C to +85 °C (Industrial) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | CMOS SRAM-based FPGA |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Type de montage | Surface Mount (PLCC J-Lead) | Through-Hole (PLCC socket) |
| Statut RoHS | unknown | [DATA_NEEDED: rohs compliance for legacy PLCC variant] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status for PCG84 PLCC package] |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Usable Gates | — | 6,000 |
| Configurable Logic Blocks (CLBs) | — | 320 |
| Tension d'alimentation | — | 3.3 V |
| Maximum Toggle Frequency | — | 80 MHz |
| Configuration Memory | — | SRAM (volatile, reload required at power-up) |
| I/O Standards | — | TTL, CMOS |
| Development Tool | — | XACT (Xilinx Classic), XC3000 design flow |
| Programmable Elements | — | IOBs, CLBs, Programmable Interconnect |
| Boundary Scan | — | Yes (per XC3000 family) |