10AS032H2F35E2SG - Arria 10 SX 320K LE SoC FPGA | Intel
Référence : 10AS032H2F35E2SG ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $1850 | $1 850,00 |
| 10 | $1695 | $16 950,00 |
| 50 | $1560 | $78 000,00 |
| 100 | $1450 | $145 000,00 |
| 500 | $1325 | $662 500,00 |
10AS032H2F35E2SG Présentation
An SoC FPGA (System-on-Chip Field-Programmable Gate Array) is a hybrid device that combines a traditional FPGA fabric with a hard processor system (HPS) on a single die, in the hierarchy FPGA -> programmable logic device -> semiconductor IC. The Arria 10 SX extends this by integrating ARM Cortex-A9 cores with tightly coupled peripherals, reducing BOM count and board area compared to a discrete CPU + FPGA design while retaining the FPGA's parallel processing flexibility for DSP, video pipelines, and custom accelerators.
Key features of the 10AS032 include 320K logic elements (LEs), transceivers supporting multi-gigabit serial I/O, on-chip memory, variable-precision DSP blocks, and hard memory controllers. The integrated HPS provides the standard ARM Cortex-A9 debug, interrupt, and memory subsystem, supporting Linux and RTOS deployments. Hard IP for PCI Express Gen2/Gen3, memory interfaces (DDR3/DDR4 with hard controllers), and partial reconfiguration further accelerate time-to-market.
The device's 20 nm process technology balances performance-per-watt with high logic density, making it well-suited for throughput-oriented embedded systems. The Arria 10 architecture includes hardened floating-point DSP blocks, which deliver up to ~1.5 TFLOPs DSP performance per device (per Intel Arria 10 device overview), enabling DSP-intensive workloads without consuming general fabric resources.
Typical applications include Software Defined Radio (SDR), video broadcasting and image processing, industrial motor control, PCIe-based accelerator cards, and military/aerospace signal processing. The SoC integration suits applications needing both an OS-managed application layer and a deterministic, parallel datapath in the FPGA fabric.
When designing with this device, ensure the PCB incorporates sufficient decoupling for the FCBGA's high-speed transceivers and proper thermal management for the 35x35 mm package. Use the Intel Quartus Prime design suite for synthesis, place-and-route, and HPS configuration. Verify that the chosen temperature grade (E2) matches the deployment environment's ambient range.
This page consolidates distributor pricing, drop-in same-package alternatives from the Arria 10 SX family, and practical design notes that complement the official datasheet for engineers evaluating the 10AS032H2F35E2SG.
Alternatives de remplacement direct pour 10AS032H2F35E2SG — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec 10AS032H2F35E2SG (même facteur de forme et même empreinte) — différant par Package, Operating Temperature Grade, Package Code, Mounting Type, Process Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
10AS032H2F35E2LG
✅ Remplacement direct✓ En stock
$2310 / unité
Voir la fiche technique →10AS032H2F35E1HG
✅ Remplacement direct✓ En stock
$1293 / unité
Voir la fiche technique →10AS032H1F35E1HG
✅ Remplacement direct✓ En stock
$2540 / unité
Voir la fiche technique →10AS032H2F34I2SG
✅ Remplacement direct✓ En stock
$3760 / unité
Voir la fiche technique →10AS032H2F34E2SG
✅ Remplacement direct✓ En stock
$1410 / unité
Voir la fiche technique →10AS032H2F34I2LG
✅ Remplacement direct✓ En stock
$1390 / unité
Voir la fiche technique →10AS032H2F34I1HG
✅ Remplacement direct✓ En stock
$2700.05 / unité
Voir la fiche technique →10AS032H2F35E2SG Valeurs maximales et caractéristiques électriques
| Series | Arria 10 SX |
| Family | 10AS032 (F35 package) |
| Core Type | Dual ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 320K |
| Core Frequency | 1.5 GHz (HPS) |
| Boîtier | 1152-FCBGA, FC (35x35 mm) |
| Nombre de broches | 1152 |
| Type de montage | Surface Mount (BGA) |
| Temperature Grade | E2 (industrial / extended) |
| Speed Grade | H2 |
| DSP Blocks | Variable-precision hardened DSP blocks |
| Transceivers | Multi-gigabit transceivers (per Arria 10 family) |
| Hard Memory Controllers | DDR3/DDR4 hard controllers |
| PCI Express | Hard IP for PCIe Gen2/Gen3 |
| Embedded Memory | On-chip M20K + MLAB memory |
| Statut RoHS | Compliant |
| Process Technology | 20 nm |
| Design Tool | Intel Quartus Prime |
Guide de configuration des broches du 10AS032H2F35E2SG 1152-fcbga, fc (35x35 mm)
Configuration des broches du 10AS032H2F35E2SG (boîtier 1152-fcbga, fc (35x35 mm)). Ce circuit intégré numérique comprend des GPIO, des interfaces de communication (UART, SPI, I2C) et des broches d'alimentation. Consultez la fiche technique du fabricant pour les fonctions alternatives des broches et les options de configuration. Indispensable pour la conception de systèmes embarqués et la conception de circuits imprimés.
Aucune donnée de brochage détaillée disponible pour 10AS032H2F35E2SG.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
10AS032H2F35E2SG convient pour 6 applications: Software Defined Radio (SDR), Video Broadcast and Image Processing, Industrial Motor Control and Drive, PCIe Accelerator Cards, Aerospace and Defense Signal Processing, Test and Measurement Instrumentation.
Software Defined Radio (SDR)
The 10AS032H2F35E2SG is a strong fit for Software Defined Radio baseband processing where the ARM Cortex-A9 HPS runs the protocol stack and OS while the 320K-logic-element FPGA fabric executes the physical-layer DSP pipeline. The device's variable-precision hardened DSP blocks handle FIR filtering, FFT/iFFT, and channelization at multi-hundred-MHz rates, while multi-gigabit transceivers interface directly to ADC/DAC JESD204B/C links. Compared with a discrete CPU+FPGA design, the integrated HPS reduces board area and latency for control-plane messaging. The E2 industrial temperature grade suits outdoor and vehicle-deployed SDR units.
Recommandé
Video Broadcast and Image Processing
Broadcast video systems, surveillance encoders, and medical imaging benefit from the 10AS032H2F35E2SG's parallel fabric for pixel-rate pipelines and the HPS for codec management. The 320K logic elements sustain 4K video processing at 60 fps with motion estimation, scaling, and color-space conversion in dedicated fabric, while the ARM cores run a Linux media stack for transport, encryption, and network output. Hardened memory controllers feed DDR3/DDR4 frame buffers at multi-gigabyte-per-second rates. The PCIe Gen2/Gen3 hard IP enables plug-in capture cards for broadcast servers.
Recommandé
Industrial Motor Control and Drive
Industrial servo drives, robotic controllers, and CNC machines deploy the 10AS032H2F35E2SG to combine deterministic FPGA-based PWM generation, encoder decoding, and field-oriented control with an HPS running real-time Ethernet stacks (EtherCAT, PROFINET) and supervisory control. The fabric executes current/voltage control loops at sub-microsecond intervals, while the dual Cortex-A9 handles network protocol, HMI, and safety logic. Industrial-grade E2 temperature rating and PCIe Gen2/Gen3 connectivity to industrial PCs make it a fit for factory-automation controllers requiring deterministic performance.
Recommandé
PCIe Accelerator Cards
The 10AS032H2F35E2SG serves as the FPGA compute engine on PCIe add-in cards for HPC, financial analytics, and database acceleration, with the HPS managing host communication, DMA, and configuration. Hard PCIe Gen3 IP provides low-latency host-to-FPGA transport at 8 GT/s, while the 320K logic elements implement custom accelerators (encryption, compression, machine-learning inference). Compared with GPU cards, FPGA accelerators deliver better performance-per-watt for specific bit-stream workloads and deterministic latency.
Recommandé
Aerospace and Defense Signal Processing
Defense radar, electronic-warfare, and avionics platforms deploy the 10AS032H2F35E2SG for high-throughput DSP with secure boot. The hardened DSP blocks execute pulse-Doppler radar FFTs and digital beamforming across thousands of channels at sample rates exceeding 1 GSPS, while the HPS handles track management, display routing, and MIL-STD-1553/Ethernet I/O. The 1152-FCBGA's robust thermal envelope suits conduction-cooled ruggedized enclosures. Industrial-grade E2 temperature and the integrated HPS reduce SWaP-C versus separate CPU and FPGA implementations.
Recommandé
Test and Measurement Instrumentation
High-end oscilloscopes, protocol analyzers, and ATE (automatic test equipment) leverage the 10AS032H2F35E2SG's parallel processing for real-time waveform analysis. The FPGA fabric performs triggering, decimation, and protocol decoding at multi-GSample rates, while the ARM HPS manages the GUI, USB/Ethernet connectivity, and disk storage. Hard DDR3/DDR4 controllers hold deep acquisition memory, and PCIe enables streaming to host workstations. Compared with dedicated ASIC-based instruments, FPGA-based platforms offer reconfigurability for evolving protocol standards.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour 10AS032H2F35E2SG — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | 10AS032H2F35E2LG | 10AS032H2F35E1HG | 10AS032H1F35E1HG | 10AS032H2F34I2SG | 10AS032H2F34E2SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FCBGA, FC (35x35) | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same |
| Logic Elements | 320K | 320K | 320K | 320K | 320K | 320K |
| Speed Grade | H2 | H2 | H2 | H1 | H2 | H2 |
| Temperature Grade | E2 (industrial) | E2 (industrial) | E1 (commercial/extended) | E1 (commercial/extended) | I2 (industrial) | E2 (industrial) |
| HPS Cores | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Design Tool | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime |
Principaux différenciateurs
- Same F35 1152-BGA land pattern as H2/E1 variant for easy grade downgrades (vs 10AS032H2F35E1HG)
- Identical F34 1152-BGA footprint across packaging-code variants (vs 10AS032H2F34I2SG)
- Higher speed grade (H2) versus H1 for tighter timing margins (vs 10AS032H1F35E1HG)
Notes de conception
Estimated: The 1152-FCBGA package at full fabric utilization and high transceiver toggle rates can dissipate 15-25 W. Use the Arria 10 Thermal Modeling Tool to estimate junction temperature; a heatsink with thermal interface material or a cold-plate is recommended for industrial E2 deployments. Ensure PCB stack-up provides adequate copper thermal mass under the BGA, with thermal vias in the central pad array. Without thermal management, junction temperature may exceed 100C in enclosed chassis.
Design PCB stack-up to the Arria 10 GX/SX Device Family High-Speed PCB Layout Guidelines. Route transceiver channels with controlled impedance (100 ohm differential for transceivers, 50 ohm SE for high-speed I/O), maintain 8-mil traces in the BGA break-out region, and use symmetric via-in-pad microvia construction. Decouple each transceiver and HPS power rail with 0.1 uF + 10 uF + 100 uF capacitors placed within the recommended distance from the BGA balls.
Do not assume the 10AS032H2F35E2SG (speed grade H2, temp grade E2) is interchangeable with H1 or E1 variants without revalidating timing closure and operating temperature. Confirm the exact OPN before PCB assembly, as Intel Arria 10 OPN suffixes encode package code, pin count, speed grade, temperature grade, and shipping media. Use Quartus Prime's device selection wizard to lock in the precise ordering code.
Route HPS DDR3/DDR4 memory interfaces with matched-length, matched-impedance traces per the Arria 10 External Memory Interface Handbook. Keep HPS JTAG and Cortex-A9 debug traces short; if using trace probes, allocate connector footprint in early PCB revisions. Separate noisy switching-power regions from sensitive transceiver and reference-clock areas.
Informations de conformité
RoHS compliant per Intel Altera product page; Arria 10 SX family is not AEC-Q100 qualified (use automotive-qualified FPGA families for that requirement).
