10AS032H2F35E2SG - Arria 10 SX 320K LE SoC FPGA | Intel
MPN: 10AS032H2F35E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1695 | $16,950.00 |
| 50 | $1560 | $78,000.00 |
| 100 | $1450 | $145,000.00 |
| 500 | $1325 | $662,500.00 |
Drop-in alternatives for 10AS032H2F35E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS032H2F35E2LG
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View Datasheet →10AS032H2F35E1HG
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View Datasheet →10AS032H1F35E1HG
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View Datasheet →10AS032H2F34I2SG
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View Datasheet →10AS032H2F34E2SG
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View Datasheet →10AS032H2F34I2LG
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View Datasheet →10AS032H2F34I1HG
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View Datasheet →10AS032H2F35E2SG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 SX |
| Family | 10AS032 (F35 package) |
| Core Type | Dual ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 320K |
| Core Frequency | 1.5 GHz (HPS) |
| Package | 1152-FCBGA, FC (35x35 mm) |
| Pin Count | 1152 |
| Mounting Type | Surface Mount (BGA) |
| Temperature Grade | E2 (industrial / extended) |
| Speed Grade | H2 |
| DSP Blocks | Variable-precision hardened DSP blocks |
| Transceivers | Multi-gigabit transceivers (per Arria 10 family) |
| Hard Memory Controllers | DDR3/DDR4 hard controllers |
| PCI Express | Hard IP for PCIe Gen2/Gen3 |
| Embedded Memory | On-chip M20K + MLAB memory |
| RoHS Status | Compliant |
| Process Technology | 20 nm |
| Design Tool | Intel Quartus Prime |
10AS032H2F35E2SG 1152-fcbga, fc (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS032H2F35E2SG (1152-fcbga, fc (35x35 mm) package) with 1152 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS032H2F35E2SG.
Refer to the datasheet for full pin configuration.
Estimated pin count: 1152 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H2F35E2SG is suitable for 6 applications: Software Defined Radio (SDR), Video Broadcast and Image Processing, Industrial Motor Control and Drive, PCIe Accelerator Cards, Aerospace and Defense Signal Processing, Test and Measurement Instrumentation.
Software Defined Radio (SDR)
The 10AS032H2F35E2SG is a strong fit for Software Defined Radio baseband processing where the ARM Cortex-A9 HPS runs the protocol stack and OS while the 320K-logic-element FPGA fabric executes the physical-layer DSP pipeline. The device's variable-precision hardened DSP blocks handle FIR filtering, FFT/iFFT, and channelization at multi-hundred-MHz rates, while multi-gigabit transceivers interface directly to ADC/DAC JESD204B/C links. Compared with a discrete CPU+FPGA design, the integrated HPS reduces board area and latency for control-plane messaging. The E2 industrial temperature grade suits outdoor and vehicle-deployed SDR units.
Recommended
Video Broadcast and Image Processing
Broadcast video systems, surveillance encoders, and medical imaging benefit from the 10AS032H2F35E2SG's parallel fabric for pixel-rate pipelines and the HPS for codec management. The 320K logic elements sustain 4K video processing at 60 fps with motion estimation, scaling, and color-space conversion in dedicated fabric, while the ARM cores run a Linux media stack for transport, encryption, and network output. Hardened memory controllers feed DDR3/DDR4 frame buffers at multi-gigabyte-per-second rates. The PCIe Gen2/Gen3 hard IP enables plug-in capture cards for broadcast servers.
Recommended
Industrial Motor Control and Drive
Industrial servo drives, robotic controllers, and CNC machines deploy the 10AS032H2F35E2SG to combine deterministic FPGA-based PWM generation, encoder decoding, and field-oriented control with an HPS running real-time Ethernet stacks (EtherCAT, PROFINET) and supervisory control. The fabric executes current/voltage control loops at sub-microsecond intervals, while the dual Cortex-A9 handles network protocol, HMI, and safety logic. Industrial-grade E2 temperature rating and PCIe Gen2/Gen3 connectivity to industrial PCs make it a fit for factory-automation controllers requiring deterministic performance.
Recommended
PCIe Accelerator Cards
The 10AS032H2F35E2SG serves as the FPGA compute engine on PCIe add-in cards for HPC, financial analytics, and database acceleration, with the HPS managing host communication, DMA, and configuration. Hard PCIe Gen3 IP provides low-latency host-to-FPGA transport at 8 GT/s, while the 320K logic elements implement custom accelerators (encryption, compression, machine-learning inference). Compared with GPU cards, FPGA accelerators deliver better performance-per-watt for specific bit-stream workloads and deterministic latency.
Recommended
Aerospace and Defense Signal Processing
Defense radar, electronic-warfare, and avionics platforms deploy the 10AS032H2F35E2SG for high-throughput DSP with secure boot. The hardened DSP blocks execute pulse-Doppler radar FFTs and digital beamforming across thousands of channels at sample rates exceeding 1 GSPS, while the HPS handles track management, display routing, and MIL-STD-1553/Ethernet I/O. The 1152-FCBGA's robust thermal envelope suits conduction-cooled ruggedized enclosures. Industrial-grade E2 temperature and the integrated HPS reduce SWaP-C versus separate CPU and FPGA implementations.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, protocol analyzers, and ATE (automatic test equipment) leverage the 10AS032H2F35E2SG's parallel processing for real-time waveform analysis. The FPGA fabric performs triggering, decimation, and protocol decoding at multi-GSample rates, while the ARM HPS manages the GUI, USB/Ethernet connectivity, and disk storage. Hard DDR3/DDR4 controllers hold deep acquisition memory, and PCIe enables streaming to host workstations. Compared with dedicated ASIC-based instruments, FPGA-based platforms offer reconfigurability for evolving protocol standards.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H2F35E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H2F35E2LG | 10AS032H2F35E1HG | 10AS032H1F35E1HG | 10AS032H2F34I2SG | 10AS032H2F34E2SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FCBGA, FC (35x35) | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same | 1152-FCBGA, FC (35x35) - same |
| Logic Elements | 320K | 320K | 320K | 320K | 320K | 320K |
| Speed Grade | H2 | H2 | H2 | H1 | H2 | H2 |
| Temperature Grade | E2 (industrial) | E2 (industrial) | E1 (commercial/extended) | E1 (commercial/extended) | I2 (industrial) | E2 (industrial) |
| HPS Cores | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Design Tool | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime | Quartus Prime |
Key Differentiators
- Same F35 1152-BGA land pattern as H2/E1 variant for easy grade downgrades (vs 10AS032H2F35E1HG)
- Identical F34 1152-BGA footprint across packaging-code variants (vs 10AS032H2F34I2SG)
- Higher speed grade (H2) versus H1 for tighter timing margins (vs 10AS032H1F35E1HG)
Design Notes
Estimated: The 1152-FCBGA package at full fabric utilization and high transceiver toggle rates can dissipate 15-25 W. Use the Arria 10 Thermal Modeling Tool to estimate junction temperature; a heatsink with thermal interface material or a cold-plate is recommended for industrial E2 deployments. Ensure PCB stack-up provides adequate copper thermal mass under the BGA, with thermal vias in the central pad array. Without thermal management, junction temperature may exceed 100C in enclosed chassis.
Design PCB stack-up to the Arria 10 GX/SX Device Family High-Speed PCB Layout Guidelines. Route transceiver channels with controlled impedance (100 ohm differential for transceivers, 50 ohm SE for high-speed I/O), maintain 8-mil traces in the BGA break-out region, and use symmetric via-in-pad microvia construction. Decouple each transceiver and HPS power rail with 0.1 uF + 10 uF + 100 uF capacitors placed within the recommended distance from the BGA balls.
Do not assume the 10AS032H2F35E2SG (speed grade H2, temp grade E2) is interchangeable with H1 or E1 variants without revalidating timing closure and operating temperature. Confirm the exact OPN before PCB assembly, as Intel Arria 10 OPN suffixes encode package code, pin count, speed grade, temperature grade, and shipping media. Use Quartus Prime's device selection wizard to lock in the precise ordering code.
Route HPS DDR3/DDR4 memory interfaces with matched-length, matched-impedance traces per the Arria 10 External Memory Interface Handbook. Keep HPS JTAG and Cortex-A9 debug traces short; if using trace probes, allocate connector footprint in early PCB revisions. Separate noisy switching-power regions from sensitive transceiver and reference-clock areas.
Compliance Information
RoHS compliant per Intel Altera product page; Arria 10 SX family is not AEC-Q100 qualified (use automotive-qualified FPGA families for that requirement).
