AD805BN - 155 Mbps Data Retiming PLL | Analog Devices
Référence : AD805BN ✗ Fin de vie| Qté | Prix unitaire | Total |
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| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
| 100 | $0 | $0,00 |
| 500 | $0 | $0,00 |
| 1 000 | $0 | $0,00 |
AD805BN Présentation
A data-retiming PLL belongs to the clock-and-timing IC hierarchy, where phase-locked loops synchronize a local oscillator to an incoming data stream and retime data against a recovered clock. The AD805BN is intended to work with a Voltage-Controlled Crystal Oscillator (VCXO), allowing an external oscillator to provide the timing reference needed by high-speed telecom or storage links. Its retiming function aligns incoming NRZ data with a recovered clock instead of merely passing data through unchanged.
The principal verified feature set includes 155 Mbps clock recovery and data retiming, CCITT G.958 Type A jitter tolerance, CCITT G.958 Type B jitter transfer, 0.6 rms random jitter, virtually eliminated pattern jitter, and fundamentally no jitter peaking. Acquisition is specified as 30 bit periods. Distributor listings identify the device as a PLL-based clock driver with one true output and one inverted output in PDIP-20 packaging.
Typical uses include telecom backplane clock recovery, high-speed serial-interface retiming, digital transmission equipment, and NRZ-based clock-recovery circuits where deterministic data timing is required. The AD805BN is not a general-purpose buffer or regulator; its design must be evaluated against the link rate, oscillator behavior, loop bandwidth, and timing budget of the complete system. Using a VCXO with the correct frequency range and control polarity is central to achieving stable lock in practical designs.
The main design consideration is to validate loop dynamics at the actual line rate and data pattern. The PLL must receive clean reference timing, while input and output interfaces require suitable termination and controlled-impedance routing. Because the provided data does not include complete voltage, supply-current, temperature, pinout, or absolute timing tables, those parameters remain marked as data needed rather than inferred.
This product page consolidates verified source snippets, application context, and engineering guidance while distinguishing confirmed AD805BN facts from parameters that require the complete manufacturer datasheet. Pricing, stock, lifecycle status, and package details should be reconfirmed with the linked suppliers before production procurement.
Alternatives de remplacement direct pour AD805BN — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
Aucune alternative de remplacement direct disponible pour ce produit.
Demander des alternativesAD805BN Valeurs maximales et caractéristiques électriques
| Fonction | Data retiming phase-locked loop |
| Maximum Clock Recovery and Data Retiming Rate | 155 Mbps |
| Data Format | Nonreturn-to-Zero (NRZ) |
| Clock Output Configuration | 1 true output and 1 inverted output |
| Random Jitter | 0.6 rms |
| Pattern Jitter | Virtually eliminated |
| Jitter Peaking | Fundamentally none |
| Acquisition Time | 30 bit periods |
| Jitter Tolerance | CCITT G.958 Type A |
| Jitter Transfer | CCITT G.958 Type B |
| Oscillator Interface | Voltage-Controlled Crystal Oscillator (VCXO) |
| Boîtier | 20-pin plastic DIP, PDIP-20 |
| Package Pitch | 0.300 in, 7.62 mm |
Guide de configuration des broches du AD805BN 0.300 in, 7.62 mm
Configuration des broches du AD805BN (boîtier 0.300 in, 7.62 mm). Ce composant analogique comporte des broches d'entrée, de sortie et d'alimentation. Consultez la fiche technique du fabricant pour les configurations des broches d'annulation d'offset, de compensation et d'activation. Idéal pour le conditionnement de signaux et les circuits amplificateurs.
Aucune donnée de brochage détaillée disponible pour AD805BN.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
AD805BN convient pour 6 applications: Telecom Backplane Clock Recovery, High-Speed NRZ Data Retiming, 155 Mbps Serial Interface, Optical Transport Card Receive Path, Digital Transmission Equipment, Legacy High-Speed Backplane.
Telecom Backplane Clock Recovery
The AD805BN fits telecom backplane links that carry NRZ data and require the receiver to retime the stream before downstream logic processes it. Its documented 155 Mbps capability and 30-bit-period acquisition provide a defined starting point for a clock-and-data-recovery stage using a VCXO. The CCITT G.958 references are especially relevant when link engineers evaluate jitter tolerance and transfer, but board-level BER, loss, and loop stability must be verified rather than inferred from the IC rating alone.
Recommandé
High-Speed NRZ Data Retiming
The AD805BN can retime NRZ data against a recovered clock in a high-speed serial interface. Its pattern-jitter performance is described as virtually eliminated, and the absence of jitter peaking helps preserve timing margin during retiming. The circuit still needs a suitable VCXO, input/output termination, controlled-impedance routing, and power filtering. Because the supplied data does not include supply voltage or logic thresholds, those values must come from the complete AD805 datasheet before implementation.
Recommandé
155 Mbps Serial Interface
The AD805BN is aimed at serial links operating up to 155 Mbps, making it relevant to telecom equipment and legacy high-speed interfaces that synchronize incoming data to a local timing reference. The one true and one inverted clock outputs provide convenient complementary clock choices when the surrounding architecture requires both polarities. Selection should be based on the complete interface timing budget, the VCXO tuning range, and the required acquisition behavior under real channel conditions.
Recommandé
Optical Transport Card Receive Path
An AD805BN can be evaluated for an optical-transport receive path where incoming NRZ data must be aligned before forwarding to a demapper, framer, or retiming logic. The device's PLL-based architecture and documented jitter characteristics help address accumulated timing variation. In practice, the optical receiver, line coding, equalization, and VCXO must be designed together; the AD805BN should not be inserted without checking polarity, logic levels, and acquisition behavior at the intended data rate.
Recommandé
Digital Transmission Equipment
The AD805BN is relevant to digital transmission systems that need a recovered clock to establish a stable sampling relationship with an NRZ stream. Its 155 Mbps target rate and 30-bit-period acquisition specification provide useful design constraints for subsystem planning. Designers should also budget for VCXO control-loop behavior, output jitter, trace skew, and connector or backplane loss. The supplied data does not state operating temperature or supply limits, so those must be verified from the manufacturer documentation.
Recommandé
Legacy High-Speed Backplane
The AD805BN may be considered in a legacy backplane that uses NRZ signaling and requires data retiming close to the receiver. The device can separate timing recovery from downstream logic by aligning data to a VCXO-supported clock reference. Its suitability depends on the actual channel loss, data pattern, source impedance, and required BER. Because the verified sources do not establish lifecycle status or current authorized inventory, this use should begin with a sourcing and technical-availability review.
Recommandé
Données de référence d'ingénierie pour AD805BN — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit |
|---|---|
| Function | Data-retiming phase-locked loop |
| Maximum Data Rate | 155 Mbps |
| Data Format | NRZ |
| Acquisition | 30 bit periods |
| Random Jitter | 0.6 rms |
| Pattern Jitter | Virtually eliminated |
| Clock Outputs | 1 true and 1 inverted |
| Package | 20-pin plastic DIP, PDIP-20, 7.62 mm pitch |
| Oscillator Interface | VCXO |
| Brand | Analog Devices |
Principaux différenciateurs
- Integrated clock recovery and data retiming (vs No verified drop-in alternative was identified)
- Documented jitter characteristics (vs No verified drop-in alternative was identified)
- Explicit high-speed acquisition target (vs No verified drop-in alternative was identified)
Notes de conception
Verify the AD805BN supply voltage, logic thresholds, and power-current limits from the complete manufacturer datasheet before assigning the VCXO, receiver, and output stages. The provided web results confirm the function and package but do not provide those electrical values. In an actual design, place bypass capacitors close to the supply pins, provide a low-impedance return path, and keep noisy switching or clock circuitry away from sensitive timing nodes until measured performance is available.
Route the data, clock, and VCXO-control nets as controlled-impedance interconnects and keep the retiming loop physically compact. The AD805BN relies on clean timing relationships for clock recovery, so unnecessary trace length, stubs, and mismatched terminations can increase jitter or disturb acquisition. Because the provided sources do not specify the official pin table or recommended layout values, confirm pin numbering and reference circuitry from the full AD805 datasheet before fabrication.
Do not treat AD805BN as a generic clock buffer or assume that a generic PLL with the same speed is interchangeable. Verify the exact 20-pin PDIP footprint, all power pins, VCXO interface, true and inverted clock outputs, and NRZ data polarity. The supplied cross-reference search did not identify a verified replacement MPN, so any substitute should pass a manufacturer-approved pinout and timing review before use.
Validate random jitter, pattern jitter, and acquisition using the intended data pattern and channel rather than relying only on headline datasheet values. The AD805BN summary reports 0.6 rms random jitter, virtually eliminated pattern jitter, and fundamentally no jitter peaking, but system measurements also include VCXO noise, power-supply ripple, reflections, and clock skew. Use eye-diagram and BER-oriented testing appropriate to the 155 Mbps target.
Informations de conformité
The supplied web results do not provide verified compliance declarations for AD805BN. Compliance status must be confirmed with Analog Devices or the authorized supplier using the exact orderable part.
