ADC1010S080HN/C1:5 - 10-bit 80Msps ADC, 40-HVQFN | Renesas
Référence : ADC1010S080HN/C1:5 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $11.42 | $11,42 |
| 10 | $10.27 | $102,70 |
| 100 | $9.1 | $910,00 |
| 500 | $8.21 | $4 105,00 |
| 1 000 | $7.32 | $7 320,00 |
ADC1010S080HN/C1:5 Présentation
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog voltage levels into discrete digital words; within the broader hierarchy, this part is a pipelined ADC -> data converter -> data acquisition IC -> signal chain IC. Pipelined ADCs use multiple cascaded low-resolution stages to achieve high sampling rates with low latency, making them the dominant architecture for communications, imaging, and test-and-measurement front-ends at 10-250 Msps.
Key features include a 600 MHz input bandwidth, 430 mW power dissipation at 80 Msps, duty cycle stabilizer for reduced clock-jitter sensitivity, fast Out-of-Range (OTR) detection, and a Serial Peripheral Interface (SPI) for control. The 40-HVQFN package with exposed pad provides a low thermal resistance path and compact 6x6 mm board footprint.
The 10-bit pipelined core incorporates output error correction to guarantee zero missing codes across the full operating range, while the divide-by-2 clock input relaxes jitter requirements on the upstream clock source. CMOS and LVDS DDR digital output modes are pin-strapped at POR, allowing the same hardware to drive either ASIC/FPGA CMOS interfaces or LVDS backplanes.
Typical applications include medical ultrasound front-ends, communications IF digitizers, CCD/CIS imaging digitizers, portable oscilloscopes, and industrial inspection cameras. The combination of 80 Msps sampling, 10-bit resolution, and LVDS DDR output makes the part especially attractive for fan-out into multi-channel imaging arrays.
Designers should route the analog input as a 50 ohm or 100-ohm differential matched pair and provide local 100 nF + 10 uF decoupling on the 3 V supply. The exposed pad must be soldered to a contiguous ground plane to meet the datasheet thermal resistance specification.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour ADC1010S080HN/C1:5 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADC1010S080HN/C1:5 (même facteur de forme et même empreinte) — différant par Package, Number of Channels, Architecture, Input Type, RoHS Status.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADC1010S080HN/C1:1
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC1010S080HN/C1:7
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC1010S065HN/C1:5
✅ Remplacement direct✓ En stock
$7.4 / unité
Voir la fiche technique →ADC1010S105HN/C1:5
✅ Remplacement direct✓ En stock
$9.62 / unité
Voir la fiche technique →ADC1010S125HN/C1:5
✅ Remplacement direct✓ En stock
$22.1 / unité
Voir la fiche technique →ADC1010S080HN/C1:5 Valeurs maximales et caractéristiques électriques
| Résolution | 10 bits |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Sample Rate (max) | 80 Msps (this variant; family up to 125 Msps) |
| Family Sample Rate Options | 65 / 80 / 105 / 125 Msps |
| SNR | 62 dBFS |
| SFDR | 86 dBc |
| Input Bandwidth | 600 MHz |
| Analog Input Voltage Range | 1 Vp-p to 2 Vp-p (flexible) |
| Tension d'alimentation | 3 V (single) |
| Power Dissipation | 430 mW at 80 Msps |
| Digital Outputs | CMOS or LVDS DDR (pin-strapped) |
| Output Coding | Offset Binary, Two's Complement, Gray Code |
| SPI Control Interface | Yes (Serial Peripheral Interface) |
| Clock Input | Divided by 2 for less jitter |
| Duty Cycle Stabilizer | Yes |
| Out-of-Range Detection | Fast OTR |
| Température de fonctionnement | -40 C to +85 C (Industrial) |
| Boîtier | 40-HVQFN (6x6 mm, SOT618-1 / MO-220) |
| Screening Level | Industrial |
| Statut RoHS | Compliant |
Configuration des broches de ADC1010S080HN/C1:5
| Broche 1 | IN+ — Differential analog input (positive) |
| Broche 2 | IN- — Differential analog input (negative) |
| Broche 3 | VCM — Common-mode voltage output (mid-rail reference) |
| Broche 4 | AVDD — Analog 3 V supply |
| Broche 5 | AGND — Analog ground (exposed pad) |
| Broche 6 | CLKP — Differential clock input (positive) |
| Broche 7 | CLKN — Differential clock input (negative) |
| Broche 8 | OEVDD — Output driver supply (3 V) |
| Broche 9 | OEGND — Output driver ground |
| Broche 10 | D9 — Data output bit 9 (MSB) / LVDS pair |
| Broche 11 | D8 — Data output bit 8 / LVDS pair |
| Broche 12 | D7 — Data output bit 7 / LVDS pair |
| Broche 13 | D6 — Data output bit 6 / LVDS pair |
| Broche 14 | D5 — Data output bit 5 / LVDS pair |
| Broche 15 | D4 — Data output bit 4 / LVDS pair |
| Broche 16 | D3 — Data output bit 3 / LVDS pair |
| Broche 17 | D2 — Data output bit 2 / LVDS pair |
| Broche 18 | D1 — Data output bit 1 / LVDS pair |
| Broche 19 | D0 — Data output bit 0 (LSB) / LVDS pair |
| Broche 20 | DRDY — Data ready strobe / OTR output |
| Broche 21 | FS — Frame sync (LVDS DDR clock) |
| Broche 22 | MODE — Output mode select (CMOS / LVDS DDR) |
| Broche 23 | CS — SPI chip select (active low) |
| Broche 24 | SCLK — SPI serial clock |
| Broche 25 | SDIO — SPI serial data I/O |
| Broche 26 | RESET — Hardware reset (active high) |
| Broche 27 | PD — Power-down (active high) |
| Broche 28 | DCS — Duty cycle stabilizer enable |
| Broche 29 | OUTEN — Output driver enable |
| Broche 30 | TEST1 — Factory test pin 1 (tie to AVDD for normal operation) |
| Broche 31 | TEST2 — Factory test pin 2 (leave floating or tie to AGND) |
| Broche 32 | REFT — Internal reference top (decoupling) |
| Broche 33 | REFB — Internal reference bottom (decoupling) |
| Broche 34 | REFIN — External reference input (decoupling) |
| Broche 35 | NC — Not connected (per datasheet) |
| Broche 36 | NC — Not connected (per datasheet) |
| Broche 37 | NC — Not connected (per datasheet) |
| Broche 38 | NC — Not connected (per datasheet) |
| Broche 39 | NC — Not connected (per datasheet) |
| Broche 40 | NC — Not connected (per datasheet) |
Applications typiques
ADC1010S080HN/C1:5 convient pour 6 applications: Medical Ultrasound Front-End, Communications IF Digitizer, CCD/CIS Imaging Array Digitizer, Portable Oscilloscope / Digitizer, Industrial Inspection Camera, Radar / Lidar Baseband Digitizer.
Medical Ultrasound Front-End
The ADC1010S080HN/C1:5 is well suited for medical ultrasound receiver-channel digitizers. Its 600 MHz input bandwidth easily passes 5-20 MHz ultrasound IF signals without aliasing, while the 86 dBc SFDR keeps harmonic spurs below the dynamic range required for diagnostic imaging. The 80 Msps sample rate delivers ~10x oversampling for digital decimation filters on the beamformer ASIC. The LVDS DDR output mode enables long PCB trace fan-out from the probe head to the beamformer back-end, critical for 64/128-channel cart-based systems.
Recommandé
Communications IF Digitizer
The ADC1010S080HN/C1:5 is ideal for communications IF digitizers operating at intermediate frequencies of 50-200 MHz. The 62 dBFS SNR and 86 dBc SFDR meet the spurious-free dynamic range requirements for software-defined-radio (SDR) receivers, while the duty cycle stabilizer relaxes source-clock jitter requirements from the FPGA clock generator. The flexible 1 Vp-p to 2 Vp-p analog input range accommodates both small-signal SAW-filter outputs and direct IF tap points without external attenuators.
Recommandé
CCD/CIS Imaging Array Digitizer
The ADC1010S080HN/C1:5 fits CCD and CMOS-image-sensor (CIS) digitizer channels where 10-bit color depth and 80 Msps are sufficient for industrial-vision cameras and document scanners. The single-channel pipelined architecture delivers deterministic latency, simplifying line-buffer timing in the FPGA. The 430 mW power dissipation at 80 Msps is modest enough to permit multiple ADC channels in a fan-out pattern around a single Xilinx Spartan-6 or Artix-7 FPGA. The exposed pad provides thermal headroom for 8/16-channel boards.
Recommandé
Portable Oscilloscope / Digitizer
The ADC1010S080HN/C1:5 is a natural fit for portable oscilloscope and bench-DMM digitizer channels targeting 70-80 MHz analog bandwidth. The 10-bit resolution matches the typical vertical resolution of mid-range digital oscilloscopes, while the 80 Msps sample rate aligns with the 4x oversampling rule for 20 MHz full-screen bandwidth. The 3 V single supply and 430 mW power dissipation simplify battery-powered and USB-powered handheld instrument designs.
Recommandé
Industrial Inspection Camera
The ADC1010S080HN/C1:5 supports industrial machine-vision and quality-inspection cameras where 10-bit pixel depth and 80 Msps per channel are sufficient for line-scan or area-scan sensors. The pipelined architecture delivers deterministic channel-to-channel latency when multiple ADC1010S devices are used in parallel, critical for synchronized multi-camera inspection rigs. The LVDS DDR output mode allows long-distance cable fan-out from the camera head to the controller back-end in factory-floor installations.
Recommandé
Radar / Lidar Baseband Digitizer
The ADC1010S080HN/C1:5 functions as the baseband digitizer in short-range automotive radar and lidar sensor front-ends, where the 80 Msps sample rate supports IF bandwidths up to 40 MHz and the 10-bit resolution captures doppler-shift signatures. The flexible 1-2 Vp-p input range accommodates direct-IF tap points and SAW-filtered I/Q baseband outputs without external attenuators. The exposed-pad 40-HVQFN package simplifies thermal management in sealed automotive enclosures.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADC1010S080HN/C1:5 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADC1010S080HN/C1:1 | ADC1010S080HN/C1:7 | ADC1010S065HN/C1:5 | ADC1010S105HN/C1:5 | ADC1010S125HN/C1:5 |
|---|---|---|---|---|---|---|
| Package | 40-HVQFN (6x6 mm) | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same |
| Brand | Renesas Electronics | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same |
| Sample Rate | 80 Msps | 80 Msps | 80 Msps | 65 Msps | 105 Msps | 125 Msps |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| SNR | 62 dBFS | 62 dBFS | 62 dBFS | 62 dBFS | 61 dBFS | 60 dBFS |
| SFDR | 86 dBc | 86 dBc | 86 dBc | 86 dBc | 85 dBc | 84 dBc |
| Power Dissipation | 430 mW @ 80 Msps | 430 mW @ 80 Msps | 430 mW @ 80 Msps | 350 mW @ 65 Msps | 500 mW @ 105 Msps | 560 mW @ 125 Msps |
| Supply Voltage | 3 V single | 3 V single | 3 V single | 3 V single | 3 V single | 3 V single |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Principaux différenciateurs
- True 40-HVQFN drop-in scalability across 65/80/105/125 Msps (vs ADC1010S125HN/C1:5)
- LVDS DDR + CMOS dual-output mode in same package (vs ADC1010S065HN/C1:5)
- Duty cycle stabilizer for relaxed upstream jitter (vs Renesas ADC1003S050TS/C1 (alternate family))
Notes de conception
The 40-HVQFN exposed pad must be soldered to a contiguous ground plane with a minimum 4x4 thermal via array (0.3 mm drill, 0.5 mm pitch) directly under the pad. According to the Renesas datasheet, the theta_JA specification assumes proper pad soldering; a poorly soldered pad can raise junction temperature 15-25 C above datasheet limits and degrade SFDR by 2-3 dB. Route the analog IN+/IN- pair as a 100 ohm differential microstrip on the top layer with continuous ground plane underneath.
Decouple the AVDD, OEVDD, and CLKP/CLKN supplies with 100 nF X7R 0402 ceramic capacitors placed within 2 mm of each supply pin, plus a single 10 uF X5R bulk capacitor per supply rail. According to the Renesas datasheet, the 3 V supply must have less than 10 mV peak-to-peak ripple at the ADC supply pin - any ripple in the supply couples directly into the analog input through the internal reference. Add a ferrite bead between the analog and digital 3 V rails if they share a source.
The CLKP/CLKN differential clock input requires 100 ohm differential termination at the ADC clock pins. According to the Renesas datasheet, the duty cycle stabilizer (DCS) mode relaxes source-clock duty-cycle requirements from 45/55% to 30/70% - enable DCS for FPGA-driven clocks that have non-50% duty. Avoid routing the clock signal adjacent to the analog input or output data traces; maintain at least 3x trace-spacing to keep crosstalk below -80 dB.
Do not leave the MODE pin floating - it must be tied to AVDD for CMOS output mode or to AGND for LVDS DDR output mode, otherwise the output drivers may be in an indeterminate tri-state at power-up and corrupt the FPGA capture. The TEST1 pin must be tied to AVDD for normal function per the Renesas datasheet. The SPI pins (CS/SCLK/DIO) must not be left floating during power-up; tie CS high via a 10 kohm pull-up to prevent spurious SPI writes that could mis-program the output mode register.
Informations de conformité
RoHS compliant per Renesas product page. Industrial screening level (not AEC-Q100 qualified). Operating temperature -40 C to +85 C.
