AT28C64B-15JC - 64Kbit Parallel EEPROM, 150ns, 32-PLCC | Microchip
Référence : AT28C64B-15JC ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $2.08 | $2,08 |
| 10 | $1.86 | $18,60 |
| 100 | $1.55 | $155,00 |
| 500 | $1.32 | $660,00 |
| 1 000 | $1.1 | $1 100,00 |
AT28C64B-15JC Présentation
A parallel EEPROM is a non-volatile memory device whose I/O architecture mirrors static RAM (SRAM) for read and write cycles but retains its contents without power. Within the broader memory hierarchy, parallel EEPROMs sit between serial EEPROMs (smaller, slower, fewer pins) and NOR flash (higher density but more complex write/erase sequencing), making them ideal for legacy parallel buses, boot ROM, configuration stores, and parameter tables that demand byte-level writes without an erase step.
Key features include automatic page-write operation up to 64 bytes per 10 ms cycle, software data protection (SDP) to lock out inadvertent writes, hardware write protection via the WP pin, and a standard JEDEC-compatible pinout that simplifies design-in. The device operates from a single 5 V supply and supports TTL-compatible inputs and outputs.
Architecturally, the AT28C64B uses Microchip's advanced non-volatile CMOS process with on-chip latches for address, data, and control, accessed like static RAM for both read and write cycles. The internal charge pump generates the high-voltage programming supply on-chip, eliminating the external VPP required by legacy EPROMs and simplifying board layout.
Typical applications include legacy industrial control firmware storage, communication equipment parameter backup, point-of-sale terminals, set-top box configuration memory, and as a direct replacement for older 27C64/2764 EPROMs in systems requiring in-system reprogrammability without UV erasure. The 32-PLCC JEDEC footprint also suits socketed designs where mechanical compatibility with through-hole PLCC sockets is required.
When designing with this part, ensure VCC decoupling with a 0.1 µF ceramic capacitor placed within 5 mm of the supply pin. For reliable page-mode writes, respect the maximum 10 ms write cycle time per 64-byte page and assert WE according to the datasheet timing diagram. The WP pin should be tied to VCC or GND through a defined logic level rather than left floating.
This page synthesizes distributor pricing, drop-in JEDEC-compatible alternatives, and practical design considerations not found in the manufacturer datasheet alone, giving engineers a single reference for sourcing, replacement, and board-level implementation of the AT28C64B-15JC.
Alternatives de remplacement direct pour AT28C64B-15JC — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
AT28C64B-15JU
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
AT28C64B-15PC
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
AT28HC64B-12JU
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
AT28C64E-15JC
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
CAT28C64B
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CAT28C64BH1312
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
AT28C64B-15JC Spécifications
| Type de mémoire | Non-volatile EEPROM (Parallel) |
| Taille de mémoire | 64 Kbit (8,192 x 8) |
| Organisation de la mémoire | 8K x 8 |
| Interface | Parallel |
| Access Time | 150 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (5 V typical) |
| Active Supply Current | 40 mA |
| Standby Supply Current | 100 µA (CMOS, deselected) |
| Power Dissipation | 220 mW (active, typical) |
| Write Cycle Time | 10 ms max per page (byte-write compatible) |
| Page Size | 64 bytes (automatic page write) |
| Data Protection | Software Data Protection (SDP), hardware WP pin |
| Température de fonctionnement | 0 °C to +70 °C (commercial, 'C' suffix) |
| Boîtier | 32-pin PLCC (J-lead, 13.97 x 11.43 mm) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (Microchip product page) |
| Lead-Free | Yes |
Configuration des broches de AT28C64B-15JC
| Broche 1 | NC — Not connected (per JEDEC 32-PLCC pinout) |
| Broche 2 | A12 — Address input bit 12 (MSB) |
| Broche 3 | A7 — Address input bit 7 |
| Broche 4 | A6 — Address input bit 6 |
| Broche 5 | A5 — Address input bit 5 |
| Broche 6 | A4 — Address input bit 4 |
| Broche 7 | A3 — Address input bit 3 |
| Broche 8 | A2 — Address input bit 2 |
| Broche 9 | A1 — Address input bit 1 |
| Broche 10 | A0 — Address input bit 0 (LSB) |
| Broche 11 | I/O0 — Data input/output bit 0 (LSB) |
| Broche 12 | I/O1 — Data input/output bit 1 |
| Broche 13 | I/O2 — Data input/output bit 2 |
| Broche 14 | GND — Ground |
| Broche 15 | I/O3 — Data input/output bit 3 |
| Broche 16 | I/O4 — Data input/output bit 4 |
| Broche 17 | I/O5 — Data input/output bit 5 |
| Broche 18 | I/O6 — Data input/output bit 6 |
| Broche 19 | I/O7 — Data input/output bit 7 (MSB) |
| Broche 20 | CE — Chip Enable (active low) |
| Broche 21 | A10 — Address input bit 10 |
| Broche 22 | OE — Output Enable (active low) |
| Broche 23 | A11 — Address input bit 11 |
| Broche 24 | A9 — Address input bit 9 |
| Broche 25 | A8 — Address input bit 8 |
| Broche 26 | NC — Not connected (per JEDEC 32-PLCC pinout) |
| Broche 27 | WE — Write Enable (active low) |
| Broche 28 | NC — Not connected (per JEDEC 32-PLCC pinout) |
| Broche 29 | WP — Write Protect (active high disables writes) |
| Broche 30 | NC — Not connected (per JEDEC 32-PLCC pinout) |
| Broche 31 | VCC — Power supply (5 V) |
| Broche 32 | NC — Not connected (per JEDEC 32-PLCC pinout) |
Applications typiques
AT28C64B-15JC convient pour 6 applications: Legacy EPROM Replacement, Industrial Control Parameter Storage, Set-Top Box Configuration Memory, Point-of-Sale Terminal Storage, Communications Equipment Boot ROM, Embedded System Configuration Backup.
Legacy EPROM Replacement
The AT28C64B-15JC is widely used as a drop-in replacement for obsolete 27C64 UV-erasable EPROMs in legacy industrial and embedded systems. Its 32-pin PLCC JEDEC pinout mirrors the 27C64 footprint, while in-system electrical erase/write eliminates the UV eraser and external VPP supply. The 64-Kbit (8K x 8) parallel organization matches the original EPROM's addressing, and 150 ns access time is compatible with most 8-bit microcontrollers running at 6 MHz or below. Software data protection (SDP) prevents accidental corruption, while the 64-byte page write dramatically simplifies firmware updates versus the byte-program algorithm of legacy EPROMs.
Recommandé
Industrial Control Parameter Storage
In PLCs, motor controllers, and process instrumentation, the AT28C64B-15JC stores calibration constants, configuration tables, and machine-specific parameters that must survive power cycling. Its 5 V single-supply operation and 100 µA CMOS standby current suit battery-backed control boards. Parallel access at 150 ns gives the host CPU fast boot-time parameter reads, and the 64-byte page-write cycle lets a controller bulk-store a new recipe or setpoint table in 10 ms without blocking the real-time task. Software data protection prevents vibration- or EMI-induced accidental writes on the factory floor.
Recommandé
Set-Top Box Configuration Memory
Set-top boxes, cable modems, and satellite receivers use the AT28C64B-15JC to store channel maps, encryption keys, customer identifiers, and last-channel memory that must persist across power cycles. The 64-Kbit density is sufficient for these configuration datasets, while parallel access allows fast reads during channel-change interrupts. Hardware write-protect (WP) via a dedicated pin lets the host CPU lock the device during bootloader execution to prevent malicious firmware downgrade, and the JEDEC 32-PLCC package is widely socketed in consumer-electronics assembly lines.
Recommandé
Point-of-Sale Terminal Storage
POS terminals and electronic cash registers use the AT28C64B-15JC for transaction logs, tax-table storage, and configuration data that must survive power failures. The 100 µA standby current prolongs battery backup time during power-loss events, and the 150 ns parallel access lets the terminal CPU read transaction data rapidly at checkout. The 64-byte page write supports efficient bulk updates of price tables and operator permissions, while software data protection secures sensitive financial data against accidental writes.
Recommandé
Communications Equipment Boot ROM
Routers, switches, PBX systems, and base-station controllers historically used the AT28C64B-15JC as a parallel boot ROM for the host processor. The 8K x 8 organization holds a complete bootloader, and the parallel bus allows zero-wait-state booting on Motorola 68000 and Intel 8051 family processors at typical clock rates. Hardware write-protect via WP lets the firmware lock the boot region after provisioning, preventing remote-code-execution attacks against the boot image. The 32-PLCC JEDEC package is socketed for field replacement and firmware upgrade.
Recommandé
Embedded System Configuration Backup
Embedded designs based on 8051, PIC, AVR, and legacy Motorola microcontrollers use the AT28C64B-15JC as a parallel non-volatile configuration store for device settings, network parameters, and user preferences. The 5 V single-supply and 8-bit parallel bus match 8-bit MCU GPIO and address spaces directly, and the 150 ns access time is invisible at typical MCU clock rates. The 10 ms page-write cycle allows atomic updates of multi-byte records (with WP assertion), and the parallel bus frees the MCU's serial peripherals for other tasks.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour AT28C64B-15JC — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | AT28C64B-15JU | AT28C64B-15PC | AT28HC64B-12JU | AT28C64E-15JC | CAT28C64B | CAT28C64BH1312 |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | onsemi | onsemi |
| Package | 32-pin PLCC (J-lead, 13.97x11.43 mm) | 32-pin PLCC - same | 32-pin PLCC - same | 32-pin PLCC - same | 32-pin PLCC - same | 32-pin PLCC - same (JEDEC) | 32-pin PLCC - same (JEDEC) |
| Memory Size | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) |
| Access Time | 150 ns | 150 ns | 150 ns | 120 ns (faster) | 150 ns | 150 ns | 150 ns |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 2.7 V to 5.5 V (wider range) | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) | -40 °C to +85 °C (industrial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) |
| Lead-Free / RoHS | Compliant (Microchip product page) | Yes (lead-free finish) | No (tin-lead) | Yes (lead-free) | Yes (lead-free) | Varies by suffix | Varies by suffix |
| Page Write Size | 64 bytes | 64 bytes | 64 bytes | 64 bytes | 64 bytes | 64 bytes | 64 bytes |
Principaux différenciateurs
- Standard JEDEC 32-PLCC pinout shared with industry-standard EPROMs (vs CAT28C64B (onsemi))
- Available in faster 120 ns and industrial temperature grades in same family (vs AT28HC64B-12JU)
- Lead-free (-JU) and standard (-PC) variants available for RoHS and legacy assemblies (vs AT28C64B-15PC)
Notes de conception
Decouple VCC (pin 31) with a 0.1 µF ceramic capacitor placed within 5 mm of the supply pin, plus a bulk 10 µF tantalum or aluminum electrolytic on the same supply rail. The AT28C64B-15JC draws 40 mA active current and 100 µA in CMOS standby; inadequate decoupling causes voltage droop during the 10 ms write cycle that can corrupt data. Multiple parallel EEPROMs sharing a supply rail should each have their own 0.1 µF bypass cap.
Route CE, OE, and WE as short, parallel traces with matched lengths to avoid skew on read/write strobes. The address and I/O lines should be grouped and routed away from switching power nodes; on PLCC layouts, place the device near the host CPU to minimize bus capacitance. Keep the PLCC socket footprint within the manufacturer's recommended land dimensions (13.97 x 11.43 mm JEDEC) and provide a guard trace tied to GND around the I/O bus for EMI-sensitive industrial environments.
Do not leave WP (pin 29) floating - tie it to VCC (write-protect enabled) or GND (writes allowed) through a 10 kΩ resistor. Floating WP can drift into the protected band and silently block firmware updates. When writing, respect the 10 ms maximum page-write cycle time and poll the toggle bit or DATA polling sequence per datasheet doc0270 timing diagram. Do not exceed VCC of 5.5 V or apply reverse polarity - the device lacks internal ESD protection beyond 2 kV HBM. Software data protection (SDP) requires the three-byte unlock sequence before each write; forgetting the sequence results in silently failed writes.
Informations de conformité
RoHS-compliant per Microchip product page. Lead-free variants available with -JU suffix. Not AEC-Q100 qualified (commercial temperature only - choose AT28C64B-15-PU industrial variant for AEC-Q100 applications if needed).
