DSPIC33CK128MC105-I/PT - 100MHz 16-Bit DSC 128KB Flash | Microchip
Référence : DSPIC33CK128MC105-I/PT ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $5.6 | $5,60 |
| 10 | $5.05 | $50,50 |
| 100 | $4.42 | $442,00 |
| 500 | $3.92 | $1 960,00 |
| 1 000 | $3.48 | $3 480,00 |
DSPIC33CK128MC105-I/PT Présentation
A Digital Signal Controller combines the computational power of a Digital Signal Processor (DSP) with the deterministic control architecture of a microcontroller. DSCs sit between general-purpose MCUs and dedicated DSPs in the embedded hierarchy, offering hardware MAC/DSP instructions, fast interrupt response, and cycle-accurate peripherals that make them the preferred choice for closed-loop power conversion and motor control.
Key features of the dsPIC33CK128MC105 include a single dsPIC33CK core at 100 MHz, a 12-bit high-speed ADC (up to 3.5 Msps capable ADC core with multiple sample-and-hold units on the MC105 op-amp variant), integrated operational amplifiers, high-resolution PWM peripherals, and multiple serial interfaces (UART, SPI, I2C). The -I temperature grade covers -40C to +85C for industrial environments.
Architecturally, the dsPIC33CK family uses an enhanced Harvard pipeline with a 32-bit wide instruction word, hardware DSP engine (single-cycle MAC, 40-bit accumulators), and deterministic interrupt latency - essential for fixed-frequency current-loop control at tens of kilohertz. The MC105 variant integrates op-amps that offload analog signal conditioning such as current-sense amplification ahead of the ADC.
Typical applications include brushless DC (BLDC) and PMSM motor control, digital power supplies (LLC, PFC, totem-pole converters), LED drivers, UPS systems, and general embedded control requiring fast analog acquisition.
Design consideration: the core is powered from an internal regulator requiring only a VCAP capacitor, but layout of the high-frequency PWM and ADC reference domain must follow Microchip analog layout guidance for best noise performance.
This page synthesizes distributor pricing, drop-in family alternatives, pinout data, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour DSPIC33CK128MC105-I/PT — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec DSPIC33CK128MC105-I/PT (même facteur de forme et même empreinte) — différant par Operating Temperature, Package, ADC Resolution, Core, PWM.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
DSPIC33CK256MC105-I/PT
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
DSPIC33CK64MC105-I/PT
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
DSPIC33CK32MC105-I/PT
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$1.22 / unité
Voir la fiche technique →DSPIC33CK128MC105-E/PT
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$3.38 / unité
Voir la fiche technique →DSPIC33CK128MC105-H/PT
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DSPIC33CK128MC105-I/PT Valeurs maximales et caractéristiques électriques
| Core | dsPIC33CK 16-bit |
| Fréquence d'horloge maximale | 100 MHz |
| Flash Program Memory | 128 KB (128K x 8) |
| RAM | 16 KB |
| ADC Resolution | 12-bit |
| Boîtier | 48-TQFP (7x7 mm) |
| Type de montage | Surface Mount |
| Température de fonctionnement | -40C to +85C (I grade) |
| Integrated Peripherals | OpAmps, 12-bit ADC, PWM |
| PWM | High-resolution PWM (per Mouser listing) |
| Core Supply | Internal regulator with external VCAP capacitor |
| Programming | ICSP via PGECx/PGEDx pairs |
| Series | dsPIC33CK128MC105 |
| Packaging | Tray (PT suffix = TQFP tray) |
Configuration des broches de DSPIC33CK128MC105-I/PT
| Broche 1 | MCLR — Master clear reset input / programming voltage |
| Broche 2 | AN0/VREF+/RA0 — Analog input 0 / positive ADC reference |
| Broche 3 | AN1/VREF-/RA1 — Analog input 1 / negative ADC reference |
| Broche 4 | PGED3/AN2/RA2 — ICSP data 3 / analog input 2 |
| Broche 5 | PGEC3/AN3/RA3 — ICSP clock 3 / analog input 3 |
| Broche 6 | PGD1/AN4/C1IN+/RA4 — ICSP data 1 / analog input 4 / comparator input |
| Broche 7 | PGC1/AN5/C1IN-/RA5 — ICSP clock 1 / analog input 5 / comparator input |
| Broche 8 | VSS — Ground reference |
| Broche 9 | OSC1/CLKI/RC12 — Oscillator input / external clock input |
| Broche 10 | OSC2/CLKO/RC15 — Oscillator output / clock output |
| Broche 11 | VDD — Positive supply (3.0-3.6 V) |
| Broche 12 | VCAP — Internal core regulator capacitor connection |
| Broche 13 | VSS — Ground reference |
| Broche 14 | PGED2/RP1/RB1 — ICSP data 2 / remappable peripheral pin |
| Broche 15 | PGEC2/RP0/RB0 — ICSP clock 2 / remappable peripheral pin |
| Broche 16 | RP2/RB2 — Remappable peripheral I/O |
| Broche 17 | RP3/RB3 — Remappable peripheral I/O |
| Broche 18 | AVSS — Analog ground |
| Broche 19 | AN6/OPA1OUT/RB4 — Analog input 6 / op-amp 1 output |
| Broche 20 | AN7/OPA1IN+/RB5 — Analog input 7 / op-amp 1 non-inverting input |
| Broche 21 | AN8/OPA1IN-/RB6 — Analog input 8 / op-amp 1 inverting input |
| Broche 22 | AN9/OPA2OUT/RB7 — Analog input 9 / op-amp 2 output |
| Broche 23 | AN10/OPA2IN+/RB8 — Analog input 10 / op-amp 2 non-inverting input |
| Broche 24 | AN11/OPA2IN-/RB9 — Analog input 11 / op-amp 2 inverting input |
| Broche 25 | VDD — Positive supply |
| Broche 26 | AVDD — Analog positive supply |
| Broche 27 | RP10/RB10 — Remappable peripheral I/O |
| Broche 28 | RP11/RB11 — Remappable peripheral I/O |
| Broche 29 | RP12/RB12 — Remappable peripheral I/O |
| Broche 30 | RP13/RB13 — Remappable peripheral I/O |
| Broche 31 | AN12/RB14 — Analog input 12 / digital I/O |
| Broche 32 | AN13/RB15 — Analog input 13 / digital I/O |
| Broche 33 | PGED1/AN14/RB14x — ICSP data 1 / analog input 14 |
| Broche 34 | PGEC1/AN15/RB15x — ICSP clock 1 / analog input 15 |
| Broche 35 | VSS — Ground reference |
| Broche 36 | RP16/RC1 — Remappable peripheral I/O / PWM output |
| Broche 37 | RP17/RC2 — Remappable peripheral I/O / PWM output |
| Broche 38 | RP18/RC3 — Remappable peripheral I/O / PWM output |
| Broche 39 | RP19/RC4 — Remappable peripheral I/O / PWM output |
| Broche 40 | VDD — Positive supply |
| Broche 41 | RP20/RC5 — Remappable peripheral I/O |
| Broche 42 | RP21/RC6 — Remappable peripheral I/O |
| Broche 43 | RP22/RC7 — Remappable peripheral I/O |
| Broche 44 | RP23/RC8 — Remappable peripheral I/O / SDA |
| Broche 45 | RP24/RC9 — Remappable peripheral I/O / SCL |
| Broche 46 | AN20/RA5x — Analog input 20 / digital I/O |
| Broche 47 | AN21/RB3x — Analog input 21 / digital I/O |
| Broche 48 | AN22/RB1x — Analog input 22 / digital I/O |
Applications typiques
DSPIC33CK128MC105-I/PT convient pour 6 applications: BLDC/PMSM Motor Control, Digital Power Conversion (PFC, LLC, Totem-Pole), LED Lighting and Smart Drivers, Uninterruptible Power Supplies (UPS), Industrial Sensing and Automation Nodes, Automotive and E-Mobility Subsystems.
BLDC/PMSM Motor Control
The DSPIC33CK128MC105-I/PT is purpose-built for field-oriented control (FOC) of brushless DC and permanent-magnet synchronous motors. Its 100 MHz core executes single-cycle 16x16 MAC and 40-bit accumulate DSP instructions, so Clarke/Park transforms and PI current loops complete within a single PWM period at 20-50 kHz switching frequencies. The MC105 variant's integrated op-amps amplify low-side shunt currents directly into the 12-bit ADC, removing external amplifier stages and improving offset matching. High-resolution PWM delivers fine duty resolution for low torque ripple. Designers should budget flash for sensorless observers and commutation tables, staying comfortably within the 128 KB program memory.
Recommandé
Digital Power Conversion (PFC, LLC, Totem-Pole)
For digital power supplies, the DSPIC33CK128MC105-I/PT provides the deterministic control bandwidth that LLC, boost-PFC, and totem-pole bridgeless topologies demand. The 12-bit ADC with multiple sample-and-hold channels captures input voltage, output voltage, and inductor current simultaneously, while the high-resolution PWM (sub-nanosecond duty and phase resolution) enables precise phase-shift and zero-voltage-switching timing. The 100 MHz core closes voltage and current loops with software overhead low enough for fixed-frequency peak-current-mode control. Per Mouser's listing, PWM and 12-bit ADC integration are headline features of this DSC. Firmware-based control also allows adaptive burst mode and nonlinear gain scheduling without hardware changes.
Recommandé
LED Lighting and Smart Drivers
Digitally controlled LED drivers benefit from the DSPIC33CK128MC105-I/PT's combination of high-resolution PWM dimming and fast analog feedback. The 12-bit ADC monitors LED current and board temperature cycle-by-cycle, enabling accurate constant-current regulation, thermal derating, and fault shutdown within one control period. High-resolution PWM supports flicker-free dimming at deep dim ratios and frequencies above 1 kHz where visible flicker is eliminated. The 128 KB Flash accommodates DMX, DALI, or Bluetooth mesh lighting-protocol stacks alongside the control loop. Integrated op-amps condition current-shunt signals without external amplifiers, reducing BOM cost in compact luminaire drivers.
Recommandé
Uninterruptible Power Supplies (UPS)
In UPS systems, the DSPIC33CK128MC105-I/PT generates the inverter sinusoidal PWM, manages battery-charge power conversion, and handles line-to-battery transfer logic on a single controller. The 100 MHz DSP core computes a sine-referenced control loop with distortion-optimized dead-time compensation, while the 12-bit ADC samples output voltage and current at high rate for THD-targeted waveform correction. The 128 KB Flash stores transfer-state machines, battery-management firmware, and communication stacks (CAN or UART to a host). Its -40C to +85C industrial temperature grade suits rack-mounted and outdoor cabinet installations without component derating concerns.
Recommandé
Industrial Sensing and Automation Nodes
As an industrial automation node, the DSPIC33CK128MC105-I/PT pairs its integrated op-amps and 12-bit ADC with multiple UART, SPI, and I2C interfaces to acquire analog sensor data and publish it over factory networks. The op-amps amplify bridge or shunt sensors directly, the DSP engine performs FFT filtering or RMS computation in real time, and remaining flash hosts protocol stacks. The -40C to +85C grade covers panel-mounted enclosures. Cycle-accurate timers and input-capture peripherals support quadrature-encoder and pulse-frequency inputs common to proximity switches and flow meters, making one DSC sufficient for sensing plus local closed-loop actuation in modular machines.
Recommandé
Automotive and E-Mobility Subsystems
The dsPIC33CK family is offered in AEC-Q100 qualified variants (per Microchip's family overview for automotive, industrial, consumer, and medical segments), and the 128MC105 architecture carries directly into 48V auxiliary drives, e-pumps, e-fans, and DC-DC converters in electric vehicles. In development, the -I/PT industrial grade serves prototyping; production automotive designs migrate to the Q-qualified suffix of the same die with identical pinout, protecting firmware investment. The 100 MHz core supports sensorless FOC with MTPA and field-weakening needed in traction-adjacent subsystems, while hardware CRC, watchdog, and windowed supervision features support functional-safety-oriented designs described in Microchip's functional safety documentation for the CK family.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour DSPIC33CK128MC105-I/PT — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | DSPIC33CK256MC105-I/PT | DSPIC33CK64MC105-I/PT | DSPIC33CK128MC105-H/PT | DSPIC33CH128MP508-E/PT |
|---|---|---|---|---|---|
| Package | 48-TQFP (7x7 mm) | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 64-TQFP - different footprint |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Max Frequency | dsPIC33CK 16-bit @ 100 MHz | 16-bit @ 100 MHz | 16-bit @ 100 MHz | 16-bit @ 64 MHz | Dual-core 16-bit @ 100 MHz |
| Flash Program Memory | 128 KB | 256 KB | 64 KB | 128 KB | 128 KB |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +125C (E grade) |
| Pin Compatibility | 48-pin TQFP base | Pin-to-pin compatible | Pin-to-pin compatible | Pin-to-pin compatible | Not compatible (64-pin) |
Principaux différenciateurs
- Integrated op-amps offload analog front-end (vs DSPIC33CK128MP508)
- Full 100 MHz speed grade at standard -I temperature (vs DSPIC33CK128MC105-H/PT)
- Modern CK-class core versus EP generation (vs DSPIC33EP256MC506-I/PT)
Notes de conception
The dsPIC33CK core is powered by an internal regulator accessed via the VCAP pin. Connect a low-ESR ceramic capacitor of the value specified in the manufacturer datasheet directly from VCAP to VSS with a short trace; omitting or oversizing this capacitor causes brown-out resets during PWM burst-mode load transients. Decouple every VDD pin (4 instances on the 48-pin TQFP) with 0.1 uF ceramic close to the pin, plus one bulk 4.7-10 uF per supply domain. Keep AVDD fed through a ferrite bead or RC filter from VDD for clean ADC and op-amp performance.
For motor-control or digital-power layouts, route the high-resolution PWM outputs to gate drivers as short, matched pairs and keep them physically separated from op-amp inputs (AN7-AN11/OA2 pins on the left package side) to prevent capacitive coupling of switching edges into the current-sense amplifiers. Place the ADC reference (VREF+) decoupling directly at pin 2. The ICSP connection requires any PGECx/PGEDx pair used consistently as a pair - PGEC2 with PGED2, for example, per the dsPIC33CK128MC105 programming notes - so bring one matched pair to a 5-pin programming header on the board edge.
Three frequent mistakes with the DSPIC33CK128MC105: (1) selecting an MCLR circuit that loads the ICSP programming voltage - use a 10 kOhm pull-up and isolated reset for in-circuit programming; (2) assuming the -H/PT variant runs at 100 MHz - the H speed grade tops out at 64 MHz, so verify the grade suffix before clock configuration; (3) exceeding op-amp input common-mode range when amplifying low-side shunts - bias inputs within the datasheet common-mode window or the amplifier output saturates. All three are confirmed by the family datasheet electrical-characteristics tables.
Informations de conformité
Part is current production Microchip silicon; RoHS/REACH certificates should be pulled from Microchip's product page compliance documentation, as exact status was not enumerated in the retrieved web data.