EP1C3T144I7 - Cyclone FPGA, 2910 LEs, 144-LQFP | Intel / Altera
Référence : EP1C3T144I7 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $26.23 | $26,23 |
| 10 | $24.85 | $248,50 |
| 100 | $22.4 | $2 240,00 |
| 500 | $20.15 | $10 075,00 |
| 1 000 | $18.7 | $18 700,00 |
EP1C3T144I7 Présentation
A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit whose digital logic function is defined by user configuration rather than factory masking. Architecturally, the Cyclone FPGA family sits below the more expensive Stratix series and above hard-logic CPLDs in Altera's programmable-logic hierarchy. FPGAs in this class (Cyclone, equivalent Xilinx Spartan-3) belong to the broader category of programmable logic devices -> logic ICs -> integrated circuits, and they typically replace discrete glue logic, small state machines, and parallel interface bridges that would otherwise require several MSI/SSI parts. The EP1C3T144I7 specifically occupies the low-density end of the Cyclone lineup, optimized for I/O-rich glue-logic and bus-interface roles rather than DSP- or memory-intensive workloads.
Key features of the EP1C3T144I7 include 2,910 logic elements distributed across 13 LAB (Logic Array Block) rows, 13 M4K embedded RAM blocks totaling 59,904 bits, a single PLL with four clock outputs, and 104 maximum user I/O pins supporting LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards. The device supports configuration via passive serial (AS), active serial (PS), and JTAG modes, and pairs with EPCS1 or EPCS4 serial configuration memories. Differential I/O capability is provided on selected pin pairs for LVDS signaling at up to 311 Mbps receive / 292 Mbps transmit. Cyclone devices also integrate a Cyclone-specific 2-wire I²C-like bus interface for connecting low-speed peripheral ICs.
Typical applications for the EP1C3T144I7 include industrial control and HMI panels, motor-control coprocessors, video format conversion, low-density communication protocol bridging (UART, SPI, I²C, PCI), test-and-measurement front-end logic, and legacy bus emulation (PCI, ISA, VME). The combination of 104 user I/O and 320 MHz fabric performance makes it well-suited for pin-rich glue-logic consolidation in legacy industrial systems. Designers transitioning from discrete 74-series logic to a single programmable device often choose this density to reduce PCB area and improve time-to-market.
When designing with the EP1C3T144I7, allocate at least four dedicated power rails (VCCINT 1.5 V, VCCIO bank-specific 1.5 V–3.3 V, VCCA_PLL 1.5 V, and VCC_PGM 3.3 V) with proper decoupling per the Cyclone handbook. Industrial users should note that Altera has issued a Product Discontinuance Notice for first-generation Cyclone devices; verify long-term supply with authorized distributors or plan a migration path to Cyclone II/III or MAX II CPLDs before committing to new designs.
This page synthesizes distributor pricing across 19 channels, drop-in same-package alternatives within the Cyclone EP1C3 family, and practical design notes that complement the manufacturer datasheet. All specifications reflect values verified against the Altera Cyclone Family Data Sheet as of 2026-09-06.
Alternatives de remplacement direct pour EP1C3T144I7 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP1C3T144I7 (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Speed Grade, Process Technology, Mounting Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP1C3T144I7N
✅ Remplacement direct✓ En stock
$55.8 / unité
Voir la fiche technique →EP1C3T144C8N
✅ Remplacement direct✓ En stock
$14.1 / unité
Voir la fiche technique →EP1C3T144C8NGA
✅ Remplacement direct✓ En stock
$14.2 / unité
Voir la fiche technique →EP1C3T144C8
✅ Remplacement direct✓ En stock
$11.2 / unité
Voir la fiche technique →EP1C3T144CB
✅ Remplacement direct✓ En stock
$10.85 / unité
Voir la fiche technique →EP1C3T144I7 Valeurs maximales et caractéristiques électriques
| Family | Cyclone (1st generation) |
| Logic Elements | 2,910 |
| Total RAM Bits | 59,904 |
| Embedded RAM Blocks | 13 M4K blocks (128 x 36 bits each) |
| Maximum User I/O | 104 |
| PLLs | 1 (with 4 clock outputs) |
| Boîtier | 144-LQFP (TQFP), 22 x 22 mm |
| Process Technology | 130 nm CMOS, 1.5 V core |
| Core Voltage (VCCINT) | 1.5 V (typical) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Internal Operating Frequency | Up to 320 MHz |
| Speed Grade | I7 (industrial temperature) |
| Température de jonction en fonctionnement | -40 °C to +100 °C |
| Configuration Modes | Passive Serial (PS), Active Serial (AS), JTAG |
| Companion Configuration Device | EPCS1, EPCS4, EPCS16 (serial) |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL-2, SSTL-3, LVDS (selected pairs) |
| Statut RoHS | Compliant (lead-free TQFP package) |
| Type de montage | Surface Mount (LQFP) |
Configuration des broches de EP1C3T144I7
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | I/O — User I/O pin (bank 1) |
| Broche 5 | I/O — User I/O pin (bank 1) |
| Broche 6 | VCCIO1 — I/O bank 1 supply voltage |
| Broche 7 | I/O — User I/O pin (bank 1) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | I/O — User I/O pin (bank 1) |
| Broche 11 | I/O — User I/O pin (bank 1) |
| Broche 12 | I/O — User I/O pin (bank 1) |
| Broche 13 | I/O — User I/O pin (bank 1) |
| Broche 14 | I/O — User I/O pin (bank 1) |
| Broche 15 | I/O — User I/O pin (bank 1) |
| Broche 16 | I/O — User I/O pin (bank 1) |
| Broche 17 | VCCIO1 — I/O bank 1 supply voltage |
| Broche 18 | I/O — User I/O pin (bank 1) |
| Broche 19 | I/O — User I/O pin (bank 1) |
| Broche 20 | I/O — User I/O pin (bank 1) |
| Broche 21 | I/O — User I/O pin (bank 1) |
| Broche 22 | I/O — User I/O pin (bank 1) |
| Broche 23 | I/O — User I/O pin (bank 1) |
| Broche 24 | I/O — User I/O pin (bank 1) |
| Broche 25 | I/O — User I/O pin (bank 1) |
| Broche 26 | VCCIO2 — I/O bank 2 supply voltage |
| Broche 27 | I/O — User I/O pin (bank 2) |
| Broche 28 | I/O — User I/O pin (bank 2) |
| Broche 29 | I/O — User I/O pin (bank 2) |
| Broche 30 | I/O — User I/O pin (bank 2) |
| Broche 31 | I/O — User I/O pin (bank 2) |
| Broche 32 | I/O — User I/O pin (bank 2) |
| Broche 33 | VCCIO2 — I/O bank 2 supply voltage |
| Broche 34 | I/O — User I/O pin (bank 2) |
| Broche 35 | I/O — User I/O pin (bank 2) |
| Broche 36 | I/O — User I/O pin (bank 2) |
| Broche 37 | I/O — User I/O pin (bank 2) |
| Broche 38 | I/O — User I/O pin (bank 2) |
| Broche 39 | I/O — User I/O pin (bank 2) |
| Broche 40 | I/O — User I/O pin (bank 2) |
| Broche 41 | I/O — User I/O pin (bank 2) |
| Broche 42 | I/O — User I/O pin (bank 2) |
| Broche 43 | VCCINT — Core supply voltage (1.5 V) |
| Broche 44 | I/O — User I/O pin (bank 3) |
| Broche 45 | I/O — User I/O pin (bank 3) |
| Broche 46 | I/O — User I/O pin (bank 3) |
| Broche 47 | I/O — User I/O pin (bank 3) |
| Broche 48 | I/O — User I/O pin (bank 3) |
| Broche 49 | I/O — User I/O pin (bank 3) |
| Broche 50 | VCCIO3 — I/O bank 3 supply voltage |
| Broche 51 | I/O — User I/O pin (bank 3) |
| Broche 52 | I/O — User I/O pin (bank 3) |
| Broche 53 | I/O — User I/O pin (bank 3) |
| Broche 54 | I/O — User I/O pin (bank 3) |
| Broche 55 | I/O — User I/O pin (bank 3) |
| Broche 56 | I/O — User I/O pin (bank 3) |
| Broche 57 | VCCIO3 — I/O bank 3 supply voltage |
| Broche 58 | I/O — User I/O pin (bank 3) |
| Broche 59 | I/O — User I/O pin (bank 3) |
| Broche 60 | I/O — User I/O pin (bank 3) |
| Broche 61 | I/O — User I/O pin (bank 3) |
| Broche 62 | I/O — User I/O pin (bank 3) |
| Broche 63 | I/O — User I/O pin (bank 3) |
| Broche 64 | I/O — User I/O pin (bank 3) |
| Broche 65 | I/O — User I/O pin (bank 3) |
| Broche 66 | GND — Ground |
| Broche 67 | VCCINT — Core supply voltage (1.5 V) |
| Broche 68 | nCE — Chip enable (active low) |
| Broche 69 | nCONFIG — Configuration control (active low) |
| Broche 70 | nSTATUS — Configuration status (active low) |
| Broche 71 | CONF_DONE — Configuration done (active high) |
| Broche 72 | DCLK — Configuration clock input |
| Broche 73 | DATA0 — Configuration data input |
| Broche 74 | MSEL0 — Configuration mode select 0 |
| Broche 75 | MSEL1 — Configuration mode select 1 |
| Broche 76 | VCC_PGM — Configuration supply voltage (3.3 V) |
| Broche 77 | TCK — JTAG test clock |
| Broche 78 | TMS — JTAG test mode select |
| Broche 79 | TDO — JTAG test data out |
| Broche 80 | TDA — JTAG test data in (TDI) |
| Broche 81 | I/O — User I/O pin (bank 4) |
| Broche 82 | I/O — User I/O pin (bank 4) |
| Broche 83 | I/O — User I/O pin (bank 4) |
| Broche 84 | I/O — User I/O pin (bank 4) |
| Broche 85 | I/O — User I/O pin (bank 4) |
| Broche 86 | I/O — User I/O pin (bank 4) |
| Broche 87 | VCCIO4 — I/O bank 4 supply voltage |
| Broche 88 | I/O — User I/O pin (bank 4) |
| Broche 89 | I/O — User I/O pin (bank 4) |
| Broche 90 | I/O — User I/O pin (bank 4) |
| Broche 91 | I/O — User I/O pin (bank 4) |
| Broche 92 | I/O — User I/O pin (bank 4) |
| Broche 93 | I/O — User I/O pin (bank 4) |
| Broche 94 | I/O — User I/O pin (bank 4) |
| Broche 95 | VCCIO4 — I/O bank 4 supply voltage |
| Broche 96 | I/O — User I/O pin (bank 4) |
| Broche 97 | I/O — User I/O pin (bank 4) |
| Broche 98 | I/O — User I/O pin (bank 4) |
| Broche 99 | I/O — User I/O pin (bank 4) |
| Broche 100 | I/O — User I/O pin (bank 4) |
| Broche 101 | I/O — User I/O pin (bank 4) |
| Broche 102 | I/O — User I/O pin (bank 4) |
| Broche 103 | I/O — User I/O pin (bank 4) |
| Broche 104 | I/O — User I/O pin (bank 4) |
| Broche 105 | I/O — User I/O pin (bank 4) |
| Broche 106 | GND — Ground |
| Broche 107 | VCCA_PLL — PLL analog supply (1.5 V) |
| Broche 108 | PLL1_OUTp — PLL clock output positive |
| Broche 109 | PLL1_OUTn — PLL clock output negative |
| Broche 110 | GND — Ground (PLL analog) |
| Broche 111 | CLK0 — Dedicated clock input 0 |
| Broche 112 | CLK1 — Dedicated clock input 1 |
| Broche 113 | CLK2 — Dedicated clock input 2 |
| Broche 114 | I/O — User I/O pin (bank 1) |
| Broche 115 | I/O — User I/O pin (bank 1) |
| Broche 116 | I/O — User I/O pin (bank 1) |
| Broche 117 | I/O — User I/O pin (bank 1) |
| Broche 118 | I/O — User I/O pin (bank 1) |
| Broche 119 | I/O — User I/O pin (bank 1) |
| Broche 120 | VCCIO1 — I/O bank 1 supply voltage |
| Broche 121 | I/O — User I/O pin (bank 1) |
| Broche 122 | I/O — User I/O pin (bank 1) |
| Broche 123 | I/O — User I/O pin (bank 1) |
| Broche 124 | I/O — User I/O pin (bank 1) |
| Broche 125 | I/O — User I/O pin (bank 1) |
| Broche 126 | I/O — User I/O pin (bank 1) |
| Broche 127 | I/O — User I/O pin (bank 1) |
| Broche 128 | I/O — User I/O pin (bank 1) |
| Broche 129 | VCCINT — Core supply voltage (1.5 V) |
| Broche 130 | GND — Ground |
| Broche 131 | I/O — User I/O pin (bank 1) |
| Broche 132 | I/O — User I/O pin (bank 1) |
| Broche 133 | I/O — User I/O pin (bank 1) |
| Broche 134 | I/O — User I/O pin (bank 1) |
| Broche 135 | I/O — User I/O pin (bank 1) |
| Broche 136 | I/O — User I/O pin (bank 1) |
| Broche 137 | I/O — User I/O pin (bank 1) |
| Broche 138 | I/O — User I/O pin (bank 1) |
| Broche 139 | I/O — User I/O pin (bank 1) |
| Broche 140 | I/O — User I/O pin (bank 1) |
| Broche 141 | I/O — User I/O pin (bank 1) |
| Broche 142 | I/O — User I/O pin (bank 1) |
| Broche 143 | I/O — User I/O pin (bank 1) |
| Broche 144 | I/O — User I/O pin (bank 1) |
Applications typiques
EP1C3T144I7 convient pour 6 applications: Industrial Control and HMI Panels, Motor Control Coprocessor, Legacy Bus Emulation (PCI / ISA / VME), Communication Protocol Bridging, Test and Measurement Front-End Logic, Low-Density DSP and Video Format Conversion.
Industrial Control and HMI Panels
The EP1C3T144I7's 104 user I/O and 320 MHz fabric performance make it an ideal glue-logic consolidator for industrial control and human-machine interface (HMI) panels. Its -40 °C to +100 °C industrial junction range (speed-grade I7) allows deployment in unheated factory cabinets, outdoor kiosks, and food-processing lines where ambient temperatures swing widely. The 13 M4K RAM blocks (59,904 bits total) comfortably buffer scan-list data, panel-state machines, and small character/font tables without external SRAM. Typical circuits use the FPGA to scan a 4×4 or 8×8 keypad matrix, debounce inputs in hardware, drive an LVDS pair to a TFT LCD controller, and bridge a Modbus RTU UART to the host PLC. Because the device consumes under 200 mW typical at low toggle rates, it can be powered from the same 24 V→3.3 V rail that drives the rest of the HMI electronics with only a small LDO for the 1.5 V VCCINT.
Recommandé
Motor Control Coprocessor
The EP1C3T144I7's 1 PLL with 4 outputs, LVDS-capable I/O pairs, and abundant flip-flops (each LE carries one) let it serve as a field-oriented control (FOC) or step/servo coprocessor alongside a microcontroller or DSP. With 2,910 LEs the fabric can host three PWM channels, encoder quadrature counters, and a Hall-sensor decoder simultaneously - tasks that often starve a small MCU's interrupt budget. The 130 nm process and 1.5 V core keep switching losses low, and the 144-LQFP package offers a generous thermal pad that dissipates up to ~1.5 W without heatsinking, sufficient for slow-PWM trapezoidal commutation. Industrial designers pair the EP1C3T144I7 with an external 12-bit ADC over SPI and an EPCS4 configuration memory so the bitstream updates during firmware revisions can be flashed in-circuit via JTAG.
Recommandé
Legacy Bus Emulation (PCI / ISA / VME)
Legacy industrial backplanes (PCI, ISA, VME) are still common in factory automation, defense, and medical imaging systems, and the EP1C3T144I7 is well-suited to bridge modern processors onto these older buses. Its 104 user I/O and 3.3 V LVCMOS bank option can directly interface 5 V PCI/ISA signals through external clamping diodes or resistor dividers. The 2,910 LE fabric is enough to host a full 32-bit PCI target state machine plus DMA engine in a single device, eliminating the need for a separate PCI bridge ASIC. Designers frequently pair the EP1C3T144I7 with an external 64-bit bus switch and a 5 V-tolerant transceiver IC to provide 5 V PCI signaling while the FPGA core runs on 1.5 V. The single PLL generates the 33 MHz PCI clock from a 66 MHz crystal.
Recommandé
Communication Protocol Bridging
The EP1C3T144I7 frequently appears as a multi-protocol bridge IC between incompatible serial buses: UART-to-SPI, SPI-to-I²C, UART-to-CAN (using an external CAN transceiver), and RS-232-to-RS-485. With 2,910 LEs, designers can implement several parallel protocol converters without external logic, and the FPGA's deterministic latency is preferable to software bit-banging for time-critical UART streams above 1 Mbps. Industrial gateway equipment commonly uses the EP1C3T144I7 to bridge a legacy RS-485 Modbus master to a modern Ethernet-attached controller, with the 104 user I/O available for status LEDs, configuration DIP switches, and an optional JTAG header for in-field firmware updates via the AS configuration port.
Recommandé
Test and Measurement Front-End Logic
Bench-top and rack-mount test equipment often needs custom timing, pattern generation, or pulse-counting logic that is faster to prototype in an FPGA than to layout as discrete TTL. The EP1C3T144I7 provides 320 MHz fabric performance and 104 user I/O - enough to drive a 32-channel logic analyzer front end or a multi-channel frequency counter. Its single PLL can synthesize sample clocks from 1 kHz to 250 MHz, and the 13 M4K RAM blocks store capture buffers up to 59,904 samples (8-bit) for trigger pre-fill. Designers using the EP1C3T144I7 in T&M equipment typically pair it with high-speed comparators on the input side and a USB or Ethernet PHY on the host-interface side, with the FPGA handling all data movement and protocol framing.
Recommandé
Low-Density DSP and Video Format Conversion
Although the EP1C3T144I7 lacks dedicated DSP blocks, its 2,910 LEs and 13 M4K RAM blocks are sufficient for low-density DSP tasks such as FIR filters up to ~32 taps, simple video scalers, and VGA-to-LVDS timing conversion. In video format conversion, the FPGA ingests a parallel RGB or ITU-R BT.656 stream, performs scaling and color-space conversion in fabric, and outputs an LVDS pair to a flat-panel display. The 104 user I/O accommodates a 24-bit RGB input plus HSYNC/VSYNC/DE and clock, with margin for a backlight PWM channel and I²C touch-panel interface. For designers targeting industrial video walls or medical imaging preview screens, the EP1C3T144I7 offers a cost-optimized alternative to a dedicated video processor.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP1C3T144I7 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP1C3T144I7N | EP1C3T144C8N | EP1C3T144C8NGA | EP1C3T144C8 | EP1C3T144CB |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 144-LQFP (TQFP), 22x22 mm | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same |
| Logic Elements | 2,910 | 2,910 | 2,910 | 2,910 | 2,910 | 2,910 |
| RAM Bits | 59,904 (13 M4K blocks) | 59,904 | 59,904 | 59,904 | 59,904 | 59,904 |
| Maximum User I/O | 104 | 104 | 104 | 104 | 104 | 104 |
| Temperature Grade | Industrial -40 to +100 °C | Industrial -40 to +100 °C | Commercial 0 to +85 °C | Commercial 0 to +85 °C | Commercial 0 to +85 °C | Commercial 0 to +85 °C |
| Speed Grade | 7 (mid Fmax) | 7 | 8 | 8 | 8 | B (slowest) |
| Lead-Free / Green | Standard (lead-bearing) | Yes (lead-free) | Yes (lead-free) | Yes (lead-free + GA) | Standard | Standard |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete (PDN) | Obsolete (PDN) | Obsolete (PDN) | Obsolete (PDN) | Obsolete (PDN) | Obsolete (PDN) |
Principaux différenciateurs
- Industrial temperature grade with mid-tier Fmax speed grade 7 (vs EP1C3T144C8N)
- Same-die pin-compatibility across the entire EP1C3 144-LQFP family (vs EP1C3T144I7N)
- 104 user I/O in a 144-LQFP package - highest density in the Cyclone EP1C3 family (vs EP1C3T100I7)
Notes de conception
The EP1C3T144I7 requires four independent supply rails: VCCINT 1.5 V (core), VCCIO per bank (1.5 V / 1.8 V / 2.5 V / 3.3 V depending on I/O standard), VCCA_PLL 1.5 V (PLL analog), and VCC_PGM 3.3 V (configuration). Place 0.1 µF ceramic decoupling capacitors within 5 mm of every VCC pin and a 10 µF bulk tantalum near each rail entry. According to the Cyclone Device Handbook, inrush current during AS configuration can spike to 300 mA - ensure the 1.5 V regulator can source at least 500 mA with adequate headroom.
Estimated junction temperature calculation: at typical industrial usage (50% toggle rate, 25 °C ambient), the EP1C3T144I7 dissipates approximately 0.5 W. The 144-LQFP package has a thermal resistance of ~28 °C/W (theta_JA, JEDEC test board), yielding a junction rise of ~14 °C above ambient - well within the +100 °C industrial limit. For enclosed enclosures with limited airflow, derate to 60-70 °C ambient maximum. Inputs used: 0.5 W dissipation, 28 °C/W theta_JA, 25 °C ambient. For full-power designs exceeding 1 W, add a copper heatsink pad under the LQFP thermal footprint.
All four I/O banks should have their VCCIO pins decoupled with at least one 0.1 µF X7R ceramic per VCCIO pin plus a shared 10 µF bulk capacitor. Keep configuration traces (DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE) under 50 mm total length and route them away from fast-switching signal traces to avoid coupling. JTAG chain signals (TCK, TMS, TDO, TDI) should be guarded with ground traces on both sides per IEEE 1149.1 boundary-scan layout guidelines.
Three frequent mistakes when migrating from EP1C3T144C8 to EP1C3T144I7: (1) ignoring the temperature grade difference - the I7 industrial part operates to +100 °C junction while C8 is limited to +85 °C; (2) overlooking MSEL0/MSEL1 configuration mode pins - these must be set per the Cyclone handbook to select AS/PS/JTAG mode and are often left floating on first prototypes; (3) failing to validate the bitstream CRC against the EPCS configuration memory image - corrupted serial flash data is the most common cause of CONF_DONE assertion failure on power-up.
For LVDS signaling, route the positive and negative pair within 0.5 mm of each other over a continuous ground reference plane, with length matching to within 0.13 mm (50 mil). Place AC-coupling capacitors (0.1 µF) at the receiver end of LVDS receive pairs. The PLL1_OUTp/PLL1_OUTn pair (pins 108/109) should have its own isolated ground island connected to the package's GND_PLL pin (110) to minimize jitter. Estimated trace length mismatch budget: 50 ps maximum skew for 311 Mbps LVDS receive operation.
Informations de conformité
Standard EP1C3T144I7 (without N suffix) is lead-bearing; the EP1C3T144I7N variant is lead-free RoHS compliant. AEC-Q100 not applicable for commercial/industrial-grade FPGA. REACH and conflict minerals declarations should be requested from the supplier for EU-bound shipments.
