EP910LI-35H - 900 Gates, 24-Macrocell Classic EPLD, 35ns PLCC-44
Référence : EP910LI-35H ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1 375,00 |
| 500 | $11.4 | $5 700,00 |
| 1 000 | $9.85 | $9 850,00 |
EP910LI-35H Présentation
An EPLD (Erasable Programmable Logic Device) is a class of one-time- or erasable-programmable CMOS logic that historically preceded modern flash-based CPLDs and FPGAs. Within the programmable logic hierarchy, EPLDs sit above discrete 22V10-style PALs (in density and macrocell richness) but below contemporary non-volatile CPLDs and SRAM-based FPGAs in raw logic capacity, I/O count, and I/O standards support. The Classic EPLD family was Altera’s flagship low-power, high-speed glue-logic platform in the 1980s and 1990s, optimized for bus arbitration, address decoding, state-machine control, and peripheral interfacing on 5 V digital boards.
Key features of the EP910LI-35H include 24 dedicated macrocells with configurable D/T/JK flip-flop behavior, a programmable AND/OR array with 36 inputs feeding the PIA, pin-compatible speed grades (tPD 12 to 40 ns) that allow easy in-family upgrades/downgrades, low CMOS standby current suitable for battery-backed systems, and JEDEC-standard programmer compatibility. The architecture separates input macrocells (with registers) from output macrocells (with feedback), enabling efficient bi-directional bus implementation without external transceivers.
Typical applications include 5 V microprocessor glue logic (address decoding, wait-state insertion, interrupt prioritization), peripheral interface controllers (PIO, UART glue, custom IEEE-488 / GPIB state machines), industrial control sequencers, military and avionics legacy systems requiring MIL-STD-883 processing, and replacement designs for end-of-life discrete SSI/MSI logic. Because the part is widely second-sourced (Rochester Electronics, etc.) it remains attractive for long-lifecycle programs.
Designers should note the EP910LI-35H is a mature, NRND/EOL part on most franchised distributor line cards; long-term programs typically procure through authorized aftermarket channels. Verify pinout (44-pin PLCC) and speed grade against the original datasheet before substituting with other -35 or -30 speed grades.
This page synthesizes distributor pricing, in-family and cross-family drop-in alternatives, and practical design notes not consolidated on the manufacturer datasheet alone.
Alternatives de remplacement direct pour EP910LI-35H — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP910LI-35H (même facteur de forme et même empreinte) — différant par Package, Family, Technology, Operating Temperature, Propagation Delay (tPD).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP910LI-35
✅ Remplacement direct✓ En stock
$25.8 / unité
Voir la fiche technique →EP910LC44-35
✅ Remplacement direct✓ En stock
$19.95 / unité
Voir la fiche technique →EP910LC-30T
✅ Remplacement direct✓ En stock
$7.1 / unité
Voir la fiche technique →EP910LC-35H
✅ Remplacement direct✓ En stock
$25 / unité
Voir la fiche technique →EP910ILC-25
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP910LI-30T
✅ Remplacement direct✓ En stock
$64.59 / unité
Voir la fiche technique →EP910LI-35H Valeurs maximales et caractéristiques électriques
| Family | Altera Classic EPLD (EP910) |
| Logic Capacity | 900 usable gates |
| Macro Cells | 24 |
| Speed Grade (tPD) | 35 ns |
| Supply Voltage (VCC) | 5 V (±10%) |
| Technology | CMOS, UV-erasable EPROM cell |
| Boîtier | 44-pin PLCC (J-lead) |
| Température de fonctionnement | -40C to +85C (industrial) |
| Programmable Interconnect | Programmable Interconnect Array (PIA) |
| Type de montage | Surface Mount |
| Statut RoHS | unknown |
| Lead-Free Option (H suffix) | Yes (H suffix) |
Configuration des broches de EP910LI-35H
| Broche 1 | I/O — Macrocell I/O pin |
| Broche 2 | I/O — Macrocell I/O pin |
| Broche 3 | I/O — Macrocell I/O pin |
| Broche 4 | I/O — Macrocell I/O pin |
| Broche 5 | I/O — Macrocell I/O pin |
| Broche 6 | I/O — Macrocell I/O pin |
| Broche 7 | I/O — Macrocell I/O pin |
| Broche 8 | I/O — Macrocell I/O pin |
| Broche 9 | I/O — Macrocell I/O pin |
| Broche 10 | I/O — Macrocell I/O pin |
| Broche 11 | I/O — Macrocell I/O pin |
| Broche 12 | GND — Ground |
| Broche 13 | I/O — Macrocell I/O pin |
| Broche 14 | I/O — Macrocell I/O pin |
| Broche 15 | I/O — Macrocell I/O pin |
| Broche 16 | I/O — Macrocell I/O pin |
| Broche 17 | I/O — Macrocell I/O pin |
| Broche 18 | I/O — Macrocell I/O pin |
| Broche 19 | I/O — Macrocell I/O pin |
| Broche 20 | I/O — Macrocell I/O pin |
| Broche 21 | I/O — Macrocell I/O pin |
| Broche 22 | I/O — Macrocell I/O pin |
| Broche 23 | I/O — Macrocell I/O pin |
| Broche 24 | GND — Ground |
| Broche 25 | I/O — Macrocell I/O pin |
| Broche 26 | I/O — Macrocell I/O pin |
| Broche 27 | I/O — Macrocell I/O pin |
| Broche 28 | I/O — Macrocell I/O pin |
| Broche 29 | I/O — Macrocell I/O pin |
| Broche 30 | I/O — Macrocell I/O pin |
| Broche 31 | I/O — Macrocell I/O pin |
| Broche 32 | I/O — Macrocell I/O pin |
| Broche 33 | I/O — Macrocell I/O pin |
| Broche 34 | I/O — Macrocell I/O pin |
| Broche 35 | I/O — Macrocell I/O pin |
| Broche 36 | VCC — +5 V supply |
| Broche 37 | I/O — Macrocell I/O pin |
| Broche 38 | I/O — Macrocell I/O pin |
| Broche 39 | I/O — Macrocell I/O pin |
| Broche 40 | I/O — Macrocell I/O pin |
| Broche 41 | I/O — Macrocell I/O pin |
| Broche 42 | I/O — Macrocell I/O pin |
| Broche 43 | I/O — Macrocell I/O pin |
| Broche 44 | I/O — Macrocell I/O pin |
Applications typiques
EP910LI-35H convient pour 6 applications: 5 V Microprocessor Glue Logic, Peripheral Interface Controller (UART/GPIO/PIO glue), Industrial Control Sequencer, Legacy Avionics / Military Replacement, Bus Address Decoder, Battery-Backed / Low-Power Embedded Control.
5 V Microprocessor Glue Logic
The EP910LI-35H is well suited to 5 V microprocessor glue-logic tasks because its 24 macrocells deliver enough D/T/JK flip-flops and product terms to replace a dozen or more discrete 74LS/74F SSI/MSI packages on a CPU board. Typical uses are address decoding, wait-state insertion, bus arbitration, interrupt prioritization, and chip-select generation for 8086/68K/i386-class host designs. The 35 ns tPD comfortably meets the 8 MHz bus cycle budgets of these legacy processors without timing-closure struggles. Industrial -40 to +85C temperature grade allows deployment in factory-floor controllers. Designers should allocate the EP910LI-35H's input pins to qualifier/clock lines and reserve macrocell flip-flops for state-machine sequencing.
Recommandé
Peripheral Interface Controller (UART/GPIO/PIO glue)
The EP910LI-35H's 24 macrocells are well matched to peripheral-interface glue logic, where it can implement custom UART state machines, parallel-I/O (PIO) controllers, and protocol adapters that would otherwise require multiple 22V10 PALs. The PIA and product-term clock network allow clean multi-state sequencing for GPIB, SCSI, or proprietary backplane protocols. The 5 V single-supply CMOS design means it can be powered directly from the same rail as the host peripheral ASICs. Designers targeting legacy industrial peripherals commonly pair the EP910LI-35H with a 16550-class UART or a Z80-family PIO; the EP910 handles interrupt steering and FIFO control while the UART does byte-level serialization.
Recommandé
Industrial Control Sequencer
Industrial control sequencers often need deterministic state-machine logic at moderate density, which is exactly the role the EP910LI-35H fills. With 24 macrocells and a programmable interconnect array, it can implement multi-step process sequencers for PLCs, conveyor controllers, and packaging-machine logic, where reliability over -40 to +85C is mandatory. The 35 ns tPD gives comfortable margin for 5 V CMOS signaling on backplanes up to a few MHz. Compared with a discrete 74LS154/74LS151 decoder tree, the EP910LI-35H shrinks the BOM and improves noise immunity through integrated CMOS design. Designers should preserve a few macrocells unused for last-minute ECO logic changes.
Recommandé
Legacy Avionics / Military Replacement
The Classic EPLD family remains in demand for legacy avionics and military programs whose original Altera designs must be re-manufactured 20-30 years after the production line closed. The EP910LI-35H, especially when sourced through Rochester Electronics (an authorized long-term stocking distributor), is the canonical drop-in for these legacy boards. It maintains the original 5 V, 24-macrocell architecture while remaining pin-compatible with 1980s-era designs that were never updated. Engineers should request the -35 speed grade as specified in the original MIL-STD-883 bill of materials, and use Rochester's factory-fresh stock to avoid counterfeit risk on EOL components.
Recommandé
Bus Address Decoder
Bus address decoders for 16- and 32-bit address spaces need fast, deterministic combinational logic with predictable propagation delay. The EP910LI-35H provides 24 macrocells and a PIA that can be programmed as a multi-output address decoder, replacing 4-6 discrete 74LS139/74LS138 decoder ICs with a single part. The 35 ns tPD is well matched to 8-12 MHz 5 V buses (e.g., ISA, STD, VME). Its CMOS EPROM cell retains the address map through power cycles without a configuration PROM, which is a meaningful simplification over SRAM-based FPGAs. Industrial -40 to +85C temperature grade allows deployment in unheated enclosures.
Recommandé
Battery-Backed / Low-Power Embedded Control
The EP910LI-35H's CMOS EPROM technology gives very low standby current, which makes it attractive for battery-backed embedded control applications that need deterministic 5 V logic even when the main supply is off. Typical roles are power-on reset sequencing, RTC alarm steering, and watchdog logic in instruments that sleep for long intervals. The 5 V supply and 24 macrocells comfortably handle typical supervisor tasks without external logic. The H-suffix lead-free finish suits modern Pb-free assembly lines. Designers should still provide decoupling caps close to VCC/GND and avoid dynamic switching in standby to maintain minimum quiescent current.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP910LI-35H — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP910LI-35 | EP910LC44-35 | EP910LC-30T | EP910LC-35H | EP910ILC-25 | EP910LI-30T |
|---|---|---|---|---|---|---|---|
| Package | 44-pin PLCC | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macro Cells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Speed Grade (tPD) | 35 ns | 35 ns | 35 ns | 30 ns (-14%) | 35 ns | 25 ns (-29%) | 30 ns (-14%) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Logic Capacity | 900 gates | 900 gates | 900 gates | 900 gates | 900 gates | 900 gates | 900 gates |
| Lead-Free Finish (H suffix) | Yes (H suffix) | No (commercial finish) | No | No | Yes | No | No |
| Match Type | — | drop-in (param match 100%) | drop-in (param match 95%) | drop-in (param match 90%) | drop-in (param match 95%) | drop-in (param match 80%) | drop-in (param match 90%) |
Principaux différenciateurs
- Industrial -40 to +85C temperature grade (vs EP910LC44-35)
- Lead-free H-suffix finish for Pb-free assembly (vs EP910LI-35)
- Established second-source stocking through Rochester Electronics (vs EP910ILC-25)
Notes de conception
Estimated: EP910LI-35H ICC active at 5 V is roughly 100-200 mA at full internal-clock operation; standby ICCSB is single-digit mA per Altera Classic datasheet. Place a 0.1 uF ceramic decoupling cap adjacent to each VCC/GND pin pair and a bulk 10 uF tantalum at the board entry. The part draws more current than modern MAX II CPLDs because of its EPROM technology, so budget 250-300 mA per device on the 5 V rail.
Use a 44-pin PLCC socket (e.g., 3M Textool or Aries) for development so the part can be removed for UV erasure; production builds may solder directly. Keep high-speed signals away from the I/O pin edges to reduce simultaneous switching noise. Provide 4-layer stackup with continuous ground plane for clean 5 V return paths; the PLCC-44 lead inductance (typically 3-5 nH per lead) can otherwise introduce ringing on fast edges.
Do not assume a '35' speed grade across vendors is identical - the EP910LC-35, EP910LI-35, and EP910LC44-35 share 35 ns tPD but differ in temperature grade and package finish. Also, EP910 is an Altera-proprietary architecture with no cross-brand pin-compatible equivalents; AMD/MMI PAL parts cannot drop-in. Verify against the original datasheet pinout before substituting. Finally, the H suffix denotes lead-free finish - if your assembly process is SnPb, request the non-H variant to avoid mixed-alloy solder joints.
Estimated: at industrial +85C ambient, the PLCC-44 package has theta_JA around 50 C/W; with internal ICC of ~150 mA, internal dissipation is ~0.75 W and junction temperature rise is ~38C, leaving margin to the 125C junction spec. For sealed enclosures with no airflow, consider derating to commercial temperature to keep Tj below 100C. No external heatsink is needed for the PLCC package.
Informations de conformité
RoHS compliance inferred from H suffix (lead-free finish). No AEC-Q100 qualification - Classic EPLD family predates automotive-grade CPLD programs. Halogen-free and conflict-minerals status not documented in the verified web data; set to unknown.