EPC22C-20 - 20-Pin Altera FPGA Configuration Device | Intel/Altera
Référence : EPC22C-20 ⚠ Dernier achat| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $12.5 | $12,50 |
| 10 | $11.25 | $112,50 |
| 100 | $9.8 | $980,00 |
| 500 | $8.5 | $4 250,00 |
| 1 000 | $7.2 | $7 200,00 |
EPC22C-20 Présentation
A configuration device (EPCS / EPC family) is a special non-volatile memory IC designed to bridge the gap between flash and FPGA configuration requirements. Unlike a generic SPI flash, an EPC device is pre-engineered for Altera FPGA protocols - the dedicated serial interface (DATA, DCLK, nCS, ASDI) is timing-aligned to Altera FPGA passive-serial configuration state machines, simplifying PCB layout and firmware loading. EPC22C devices fit in the broader taxonomy: configuration memory -> non-volatile memory -> memory IC -> semiconductor.
Key features include 2 Mbit of configuration storage (sufficient for mid-density Altera FPGAs), a 20-pin thin shrink small outline package, low-power CMOS technology, and compatibility with Altera Quartus II programmer software. The "-20" suffix designates the 20-pin package option. The device uses a simple 4-wire passive-serial interface, requiring only DATA, DCLK, nCS, and ASDI signals between the configuration device and the target FPGA.
Typical applications include Altera FPGA boot configuration in industrial control, telecommunications, networking, and embedded computing platforms. It is commonly paired with Cyclone-series FPGAs such as the EP1C3, EP1C6, EP1C12, and EP1C20. The EPC22C-20 sits on the same JTAG chain as the target FPGA, allowing in-system programming through the Altera ByteBlaster or USB-Blaster download cable.
When designing with this device, ensure proper decoupling of the 3.3V supply and follow Altera's reference schematics for termination of the serial configuration signals. Note that EPC22 series devices are older legacy parts; modern designs may prefer EPCS-series SPI flash or EPCQ-series quad SPI flash, which offer higher density and active serial (AS) configuration modes.
This page synthesizes distributor availability, package information, drop-in alternative part numbers, and design considerations not consolidated on the manufacturer datasheet, helping engineers source or replace the EPC22C-20 quickly.
Alternatives de remplacement direct pour EPC22C-20 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPC22C-20 (même facteur de forme et même empreinte) — différant par Package, Supply Voltage, Mounting Type, Configuration Interface, Manufacturer.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPC2-LC20
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPC1441LC20
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPC1LC20
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$7.95 / unité
Voir la fiche technique →EPC22C-20 Valeurs maximales et caractéristiques électriques
| Fonction | FPGA configuration memory device |
| Family | EPC22C Configuration Devices |
| Compatible FPGA Series | Altera SRAM-based LUT devices (APEX, FLEX, ACEX, Cyclone, Mercury, Excalibur) |
| Interface | Passive Serial (DATA, DCLK, nCS, ASDI) |
| Tension d'alimentation | 3.3 V |
| Nombre de broches | 20 |
| Programming Interface | JTAG-compatible via ByteBlaster/USB-Blaster |
| Type de montage | Surface Mount |
| Process Technology | CMOS |
| Manufacturer | Altera (now Intel Programmable Solutions Group) |
Configuration des broches de EPC22C-20
| Broche 1 | VCC — 3.3V power supply |
| Broche 2 | GND — Ground |
| Broche 3 | DATA — Configuration data output to FPGA |
| Broche 4 | DCLK — Configuration clock input from FPGA |
| Broche 5 | nCS — Chip select (active low) |
| Broche 6 | ASDI — Serial data input from FPGA |
| Broche 7 | nCONFIG — Configuration control |
| Broche 8 | nSTATUS — Configuration status output |
| Broche 9 | TCK — JTAG test clock |
| Broche 10 | TMS — JTAG test mode select |
| Broche 11 | TDI — JTAG test data input |
| Broche 12 | TDO — JTAG test data output |
| Broche 13 | OE — Output enable |
| Broche 14 | nCE — Chip enable (active low) |
| Broche 15 | [DATA_NEEDED] — Pin function not specified in verified data |
| Broche 16 | [DATA_NEEDED] — Pin function not specified in verified data |
| Broche 17 | [DATA_NEEDED] — Pin function not specified in verified data |
| Broche 18 | [DATA_NEEDED] — Pin function not specified in verified data |
| Broche 19 | [DATA_NEEDED] — Pin function not specified in verified data |
| Broche 20 | [DATA_NEEDED] — Pin function not specified in verified data |
Applications typiques
EPC22C-20 convient pour 7 applications: Cyclone FPGA Boot Configuration, ACEX 1K FPGA Configuration, Industrial Control System FPGA, Telecommunications Line Card, Embedded Computing Platform Boot, Test and Measurement Equipment, Legacy Altera Design Maintenance.
Cyclone FPGA Boot Configuration
The EPC22C-20 stores the configuration bitstream for Altera Cyclone-series FPGAs (EP1C3, EP1C6, EP1C12, EP1C20) and loads it at power-up via the 4-wire passive-serial interface (DATA, DCLK, nCS, ASDI). Its 2 Mbit-class storage is sufficient for mid-density Cyclone designs, and the 3.3V supply matches the FPGA's VCCIO without level shifting. Placement is on the same JTAG chain as the target FPGA, enabling in-system reprogramming via USB-Blaster. This is the canonical application cited in the Altera Configuration Devices Handbook.
Recommandé
ACEX 1K FPGA Configuration
The EPC22C-20 is suited for Altera ACEX 1K family FPGAs such as EP1K10, EP1K30, and EP1K100. The passive-serial interface timing is compatible with ACEX configuration state machines, allowing direct connection without glue logic. ACEX 1K devices operate at 2.5V core with 3.3V I/O, so the EPC22C-20's 3.3V supply aligns with the FPGA's I/O bank. The 20-pin package keeps the configuration circuit compact on industrial ACEX-based control boards.
Recommandé
Industrial Control System FPGA
In industrial automation PLCs and motor controllers built on Altera Cyclone or ACEX FPGAs, the EPC22C-20 reliably stores the configuration bitstream and ensures deterministic power-up behavior. The CMOS process and 3.3V operation deliver low standby current, suitable for 24V industrial bus systems with on-board 3.3V regulation. JTAG programming support allows field firmware updates without removing the board from the chassis, critical for installed industrial equipment.
Recommandé
Telecommunications Line Card
The EPC22C-20 is used in legacy telecom line cards based on Altera APEX or Mercury FPGAs. The passive-serial interface minimizes pin usage on the FPGA, freeing I/O for data path functions. The 20-pin SOIC footprint suits dense line-card PCB layouts where vertical space is limited. JTAG chain compatibility allows the FPGA and configuration device to share a single download cable during board bring-up and field service.
Recommandé
Embedded Computing Platform Boot
The EPC22C-20 boots embedded SBCs and COM (computer-on-module) designs that use Altera Cyclone FPGAs as co-processors or glue logic. The configuration device is placed adjacent to the FPGA on the carrier board, with short trace lengths to the configuration signals to meet the DCLK timing requirements. The 3.3V supply matches standard SBC power rails, simplifying power tree design.
Recommandé
Test and Measurement Equipment
In T&M instruments such as logic analyzers, protocol testers, and bench instrumentation built on Altera FPGAs, the EPC22C-20 stores the configuration bitstream and supports rapid JTAG-driven firmware updates during product development. Its 3.3V operation is compatible with typical instrument power architectures, and the 20-pin package fits within the dense analog/digital mixed-signal PCBs common in T&M equipment.
Recommandé
Legacy Altera Design Maintenance
The EPC22C-20 supports maintenance of legacy Altera FPGA-based products where the original configuration device must be replaced without firmware redesign. By using the same passive-serial interface and pin assignments as older EPC devices, the EPC22C-20 enables form-fit-function replacement on existing boards. This is the primary reason EPC22C-20 is still sourced in 2026 - supporting installed base products.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPC22C-20 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPC2-LC20 | EPC1441LC20 | EPC1LC20 |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Interface | Passive Serial | Passive Serial | Passive Serial | Passive Serial |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Compatible FPGA Family | Cyclone / ACEX / APEX | APEX II / Mercury / FLEX | FLEX 6K/10K (smaller) | FLEX / ACEX |
| JTAG Programming | Yes | Yes | Yes | Yes |
| Lifecycle Status | Last Time Buy | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL |
| Unit Price (qty 1) | $12.50 USD | $15-25 USD (market-dependent) | $5-10 USD (market-dependent) | $8-15 USD (market-dependent) |
Principaux différenciateurs
- Legacy Altera passive-serial interface compatibility (vs EPCS4 / EPCQ4)
- Higher density than EPC1-series predecessors (vs EPC1LC20)
- Cyclone family optimization (vs EPC2-LC20)
Notes de conception
The EPC22C-20 operates from a single 3.3V supply and draws low standby current typical of CMOS configuration memory. Place a 0.1uF decoupling capacitor close to the VCC pin and a bulk 10uF tantalum or ceramic capacitor at the supply input. Ensure the 3.3V rail is stable before the FPGA's nCONFIG signal is released; Altera recommends a power-on reset sequence where the configuration device is held in reset until the supply settles within tolerance.
Route the four configuration signals (DATA, DCLK, nCS, ASDI) as short, matched-length traces between the EPC22C-20 and the target Altera FPGA. Keep these traces away from high-speed switching signals and noisy power planes. The DCLK line carries the configuration clock and must be length-matched to DATA per Altera's Configuration Devices Handbook. Use a single ground plane under the configuration section to maintain signal integrity.
Do not confuse the EPC22C-20 (passive-serial configuration) with modern EPCS/EPCQ devices (active-serial SPI configuration). They use different interfaces and FPGA MSEL pin settings. When migrating a design from EPC22C-20 to EPCS4 or EPCQ4, the FPGA's MSEL pins must be reconfigured for AS mode, the Quartus programmer settings must be updated, and the firmware must be regenerated. Also note that EPC22 series devices are in Last Time Buy - design new products around modern EPCQ-series flash.
Informations de conformité
Compliance information not present in verified distributor data. The EPC22C-20 is a legacy Altera part - refer to the manufacturer datasheet or Intel's product compliance documentation for current RoHS/REACH status.
