Altera

EPF10K10TI144-4N - FLEX 10K FPGA 10K Gates 576 Cells 144-LQFP | Intel / Altera

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5 V Vdss 144-LQFP (TQFP, T144) Package -4 (~125 MHz internal) Speed

À partir de $39.95 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-11

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$59.55	$59,55
10	$56.4	$564,00
100	$50.2	$5 020,00
500	$44.8	$22 400,00
1 000	$39.95	$39 950,00

ℹ️ Tous les prix sont en USD

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EPF10K10TI144-4N Présentation

The Intel (formerly Altera) EPF10K10TI144-4N is a member of the FLEX 10K family of Field-Programmable Gate Arrays (FPGAs), delivering 10,000 typical gates and 576 logic elements in a 144-pin LQFP (TQFP) surface-mount package with 102 user I/O pins. The device is built on a 0.42 µm CMOS SRAM process and operates from a 5 V supply, with a -4 speed grade targeting approximately 125 MHz internal performance.

A Field-Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that allows designers to configure digital logic blocks and interconnect via a hardware description language or schematic after manufacturing. Within the broader semiconductor taxonomy, the FLEX 10K family sits in the hierarchy PLD -> CPLD/FPGA -> SRAM-based FPGA -> embedded array block (EAB) FPGA, and was Altera's first family to combine look-up-table (LUT) logic with embedded array blocks for on-chip memory and arithmetic functions, enabling System-on-a-Programmable-Chip (SOPC) integration.

Key features of the EPF10K10TI144-4N include 72 Logic Array Blocks (LABs), 576 logic cells, 6,144 bits of embedded memory organized into three Embedded Array Blocks (EABs), 102 user I/O pins with individually controllable direction, and six dedicated low-skew global input pins for clock, clear, preset, output-enable, and clock-enable distribution. The 'N' suffix denotes a lead-free / industrial-grade plastic TQFP package, while the 'I' in 'TI144' indicates the industrial temperature range.

The architecture pairs fine-grain logic for combinatorial and registered paths with coarse-grain EABs sized to implement RAM, ROM, FIFO, or multiplier functions. Configuration data is loaded from an external serial or parallel PROM into on-chip SRAM latches at every power-up, making the device in-system reconfigurable but volatile. JTAG (IEEE 1149.1) boundary-scan support is included for board-level test access.

Typical applications for the EPF10K10TI144-4N include legacy glue-logic and bus-interface bridges in industrial control, telecommunications line cards, prototyping platforms for ASIC verification, and educational or test-and-measurement equipment. Because the part is now mature, it is most often specified for maintenance of long-life installed systems rather than new greenfield designs.

When designing with this device, plan around the 5 V I/O tolerance and use a dedicated configuration PROM such as the EPC2 or EPC8 family. Programming requires legacy Altera Quartus II (version 9.1 or earlier) or the MAX+PLUS II toolchain; modern Quartus versions do not target FLEX 10K. Pay close attention to the SameFrame pin-migration rules in the FLEX 10K datasheet so that any future migration to a higher-density device (e.g., EPF10K100) preserves board layout.

This page synthesizes distributor pricing across DigiKey, Mouser, Heisener and Octopart, drop-in same-package alternatives from the FLEX 10K family, and practical design notes that are not collected in any single manufacturer datasheet.

Alternatives de remplacement direct pour EPF10K10TI144-4N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPF10K10TI144-4N (même facteur de forme et même empreinte) — différant par Package, Process Technology, Operating Temperature, RoHS Status, Speed Grade.

EPF10K10ATC144-3N

Intel

Package: 144-pin TQFP (LQFP, 144-LQFP)

Process Technology: 0.3 µm CMOS

Operating Temperature: 0 °C to 70 °C (commercial)